mirror of https://github.com/F-Stack/f-stack.git
429 lines
13 KiB
C
429 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2022 Intel Corporation
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*/
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#ifndef _IDPF_LAN_TXRX_H_
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#define _IDPF_LAN_TXRX_H_
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#ifndef __KERNEL__
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#include "idpf_osdep.h"
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#endif
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enum idpf_rss_hash {
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/* Values 0 - 28 are reserved for future use */
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IDPF_HASH_INVALID = 0,
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IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29,
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IDPF_HASH_NONF_MULTICAST_IPV4_UDP,
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IDPF_HASH_NONF_IPV4_UDP,
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IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK,
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IDPF_HASH_NONF_IPV4_TCP,
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IDPF_HASH_NONF_IPV4_SCTP,
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IDPF_HASH_NONF_IPV4_OTHER,
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IDPF_HASH_FRAG_IPV4,
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/* Values 37-38 are reserved */
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IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39,
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IDPF_HASH_NONF_MULTICAST_IPV6_UDP,
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IDPF_HASH_NONF_IPV6_UDP,
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IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK,
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IDPF_HASH_NONF_IPV6_TCP,
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IDPF_HASH_NONF_IPV6_SCTP,
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IDPF_HASH_NONF_IPV6_OTHER,
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IDPF_HASH_FRAG_IPV6,
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IDPF_HASH_NONF_RSVD47,
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IDPF_HASH_NONF_FCOE_OX,
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IDPF_HASH_NONF_FCOE_RX,
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IDPF_HASH_NONF_FCOE_OTHER,
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/* Values 51-62 are reserved */
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IDPF_HASH_L2_PAYLOAD = 63,
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IDPF_HASH_MAX
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};
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/* Supported RSS offloads */
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#define IDPF_DEFAULT_RSS_HASH ( \
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BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \
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BIT_ULL(IDPF_HASH_FRAG_IPV4) | \
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BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \
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BIT_ULL(IDPF_HASH_FRAG_IPV6) | \
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BIT_ULL(IDPF_HASH_L2_PAYLOAD))
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/* TODO: Wrap below comment under internal flag
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* Below 6 pcktypes are not supported by FVL or older products
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* They are supported by FPK and future products
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*/
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#define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \
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BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \
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BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \
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BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \
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BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \
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BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \
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BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))
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/* For idpf_splitq_base_tx_compl_desc */
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#define IDPF_TXD_COMPLQ_GEN_S 15
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#define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S)
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#define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11
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#define IDPF_TXD_COMPLQ_COMPL_TYPE_M \
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MAKEMASK(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S)
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#define IDPF_TXD_COMPLQ_QID_S 0
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#define IDPF_TXD_COMPLQ_QID_M MAKEMASK(0x3FFUL, IDPF_TXD_COMPLQ_QID_S)
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/* For base mode TX descriptors */
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#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23
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#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)
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#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19
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#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \
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(0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S)
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#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12
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#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \
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(0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S)
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#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11
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#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \
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BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)
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#define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \
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IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M
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#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9
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#define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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#define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \
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(0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S)
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \
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(0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S)
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#define IDPF_TXD_CTX_QW1_MSS_S 50
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#define IDPF_TXD_CTX_QW1_MSS_M \
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MAKEMASK(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S)
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#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30
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#define IDPF_TXD_CTX_QW1_TSO_LEN_M \
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MAKEMASK(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S)
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#define IDPF_TXD_CTX_QW1_CMD_S 4
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#define IDPF_TXD_CTX_QW1_CMD_M \
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MAKEMASK(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S)
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#define IDPF_TXD_CTX_QW1_DTYPE_S 0
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#define IDPF_TXD_CTX_QW1_DTYPE_M \
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MAKEMASK(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S)
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#define IDPF_TXD_QW1_L2TAG1_S 48
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#define IDPF_TXD_QW1_L2TAG1_M \
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MAKEMASK(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S)
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#define IDPF_TXD_QW1_TX_BUF_SZ_S 34
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#define IDPF_TXD_QW1_TX_BUF_SZ_M \
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MAKEMASK(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S)
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#define IDPF_TXD_QW1_OFFSET_S 16
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#define IDPF_TXD_QW1_OFFSET_M \
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MAKEMASK(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S)
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#define IDPF_TXD_QW1_CMD_S 4
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#define IDPF_TXD_QW1_CMD_M MAKEMASK(0xFFFUL, IDPF_TXD_QW1_CMD_S)
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#define IDPF_TXD_QW1_DTYPE_S 0
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#define IDPF_TXD_QW1_DTYPE_M MAKEMASK(0xFUL, IDPF_TXD_QW1_DTYPE_S)
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/* TX Completion Descriptor Completion Types */
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#define IDPF_TXD_COMPLT_ITR_FLUSH 0
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#define IDPF_TXD_COMPLT_RULE_MISS 1
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#define IDPF_TXD_COMPLT_RS 2
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#define IDPF_TXD_COMPLT_REINJECTED 3
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#define IDPF_TXD_COMPLT_RE 4
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#define IDPF_TXD_COMPLT_SW_MARKER 5
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enum idpf_tx_desc_dtype_value {
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IDPF_TX_DESC_DTYPE_DATA = 0,
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IDPF_TX_DESC_DTYPE_CTX = 1,
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IDPF_TX_DESC_DTYPE_REINJECT_CTX = 2,
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IDPF_TX_DESC_DTYPE_FLEX_DATA = 3,
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IDPF_TX_DESC_DTYPE_FLEX_CTX = 4,
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IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX = 5,
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IDPF_TX_DESC_DTYPE_FLEX_TSYN_L2TAG1 = 6,
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IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 = 7,
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IDPF_TX_DESC_DTYPE_FLEX_TSO_L2TAG2_PARSTAG_CTX = 8,
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IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_SA_TSO_CTX = 9,
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IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_SA_CTX = 10,
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IDPF_TX_DESC_DTYPE_FLEX_L2TAG2_CTX = 11,
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IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE = 12,
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IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_TSO_CTX = 13,
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IDPF_TX_DESC_DTYPE_FLEX_HOSTSPLIT_CTX = 14,
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/* DESC_DONE - HW has completed write-back of descriptor */
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IDPF_TX_DESC_DTYPE_DESC_DONE = 15,
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};
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enum idpf_tx_ctx_desc_cmd_bits {
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IDPF_TX_CTX_DESC_TSO = 0x01,
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IDPF_TX_CTX_DESC_TSYN = 0x02,
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IDPF_TX_CTX_DESC_IL2TAG2 = 0x04,
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IDPF_TX_CTX_DESC_RSVD = 0x08,
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IDPF_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
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IDPF_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
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IDPF_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
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IDPF_TX_CTX_DESC_SWTCH_VSI = 0x30,
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IDPF_TX_CTX_DESC_FILT_AU_EN = 0x40,
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IDPF_TX_CTX_DESC_FILT_AU_EVICT = 0x80,
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IDPF_TX_CTX_DESC_RSVD1 = 0xF00
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};
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enum idpf_tx_desc_len_fields {
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/* Note: These are predefined bit offsets */
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IDPF_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
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IDPF_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
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IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
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};
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#define IDPF_TXD_QW1_MACLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S)
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#define IDPF_TXD_QW1_IPLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S)
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#define IDPF_TXD_QW1_L4LEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)
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#define IDPF_TXD_QW1_FCLEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)
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enum idpf_tx_base_desc_cmd_bits {
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IDPF_TX_DESC_CMD_EOP = 0x0001,
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IDPF_TX_DESC_CMD_RS = 0x0002,
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/* only on VFs else RSVD */
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IDPF_TX_DESC_CMD_ICRC = 0x0004,
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IDPF_TX_DESC_CMD_IL2TAG1 = 0x0008,
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IDPF_TX_DESC_CMD_RSVD1 = 0x0010,
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IDPF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
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IDPF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
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IDPF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
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IDPF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
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IDPF_TX_DESC_CMD_RSVD2 = 0x0080,
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IDPF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
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IDPF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
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IDPF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
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IDPF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
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IDPF_TX_DESC_CMD_RSVD3 = 0x0400,
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IDPF_TX_DESC_CMD_RSVD4 = 0x0800,
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};
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/* Transmit descriptors */
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/* splitq tx buf, singleq tx buf and singleq compl desc */
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struct idpf_base_tx_desc {
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__le64 buf_addr; /* Address of descriptor's data buf */
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__le64 qw1; /* type_cmd_offset_bsz_l2tag1 */
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};/* read used with buffer queues*/
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struct idpf_splitq_tx_compl_desc {
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/* qid=[10:0] comptype=[13:11] rsvd=[14] gen=[15] */
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__le16 qid_comptype_gen;
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union {
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__le16 q_head; /* Queue head */
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__le16 compl_tag; /* Completion tag */
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} q_head_compl_tag;
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u32 rsvd;
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};/* writeback used with completion queues*/
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/* Context descriptors */
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struct idpf_base_tx_ctx_desc {
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struct {
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__le32 tunneling_params;
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__le16 l2tag2;
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__le16 rsvd1;
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} qw0;
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__le64 qw1; /* type_cmd_tlen_mss/rt_hint */
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};
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/* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */
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enum idpf_tx_flex_desc_cmd_bits {
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IDPF_TX_FLEX_DESC_CMD_EOP = 0x01,
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IDPF_TX_FLEX_DESC_CMD_RS = 0x02,
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IDPF_TX_FLEX_DESC_CMD_RE = 0x04,
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IDPF_TX_FLEX_DESC_CMD_IL2TAG1 = 0x08,
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IDPF_TX_FLEX_DESC_CMD_DUMMY = 0x10,
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IDPF_TX_FLEX_DESC_CMD_CS_EN = 0x20,
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IDPF_TX_FLEX_DESC_CMD_FILT_AU_EN = 0x40,
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IDPF_TX_FLEX_DESC_CMD_FILT_AU_EVICT = 0x80,
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};
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struct idpf_flex_tx_desc {
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__le64 buf_addr; /* Packet buffer address */
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struct {
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__le16 cmd_dtype;
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#define IDPF_FLEX_TXD_QW1_DTYPE_S 0
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#define IDPF_FLEX_TXD_QW1_DTYPE_M \
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MAKEMASK(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S)
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#define IDPF_FLEX_TXD_QW1_CMD_S 5
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#define IDPF_FLEX_TXD_QW1_CMD_M MAKEMASK(0x7FFUL, IDPF_TXD_QW1_CMD_S)
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union {
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */
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u8 raw[4];
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSYN_L2TAG1 (0x06) */
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struct {
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__le16 l2tag1;
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u8 flex;
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u8 tsync;
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} tsync;
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/* DTYPE=IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 (0x07) */
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struct {
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__le16 l2tag1;
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__le16 l2tag2;
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} l2tags;
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} flex;
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__le16 buf_size;
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} qw1;
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};
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struct idpf_flex_tx_sched_desc {
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__le64 buf_addr; /* Packet buffer address */
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE_16B (0x0C) */
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struct {
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u8 cmd_dtype;
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#define IDPF_TXD_FLEX_FLOW_DTYPE_M 0x1F
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#define IDPF_TXD_FLEX_FLOW_CMD_EOP 0x20
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#define IDPF_TXD_FLEX_FLOW_CMD_CS_EN 0x40
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#define IDPF_TXD_FLEX_FLOW_CMD_RE 0x80
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u8 rsvd[3];
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__le16 compl_tag;
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__le16 rxr_bufsize;
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#define IDPF_TXD_FLEX_FLOW_RXR 0x4000
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#define IDPF_TXD_FLEX_FLOW_BUFSIZE_M 0x3FFF
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} qw1;
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};
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/* Common cmd fields for all flex context descriptors
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* Note: these defines already account for the 5 bit dtype in the cmd_dtype
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* field
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*/
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enum idpf_tx_flex_ctx_desc_cmd_bits {
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IDPF_TX_FLEX_CTX_DESC_CMD_TSO = 0x0020,
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IDPF_TX_FLEX_CTX_DESC_CMD_TSYN_EN = 0x0040,
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IDPF_TX_FLEX_CTX_DESC_CMD_L2TAG2 = 0x0080,
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IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_UPLNK = 0x0200, /* 2 bits */
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IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_LOCAL = 0x0400, /* 2 bits */
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IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_TARGETVSI = 0x0600, /* 2 bits */
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};
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/* Standard flex descriptor TSO context quad word */
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struct idpf_flex_tx_tso_ctx_qw {
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__le32 flex_tlen;
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#define IDPF_TXD_FLEX_CTX_TLEN_M 0x3FFFF
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#define IDPF_TXD_FLEX_TSO_CTX_FLEX_S 24
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__le16 mss_rt;
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#define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF
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u8 hdr_len;
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u8 flex;
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};
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union idpf_flex_tx_ctx_desc {
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_CTX (0x04) */
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struct {
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u8 qw0_flex[8];
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struct {
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__le16 cmd_dtype;
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__le16 l2tag1;
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u8 qw1_flex[4];
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} qw1;
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} gen;
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX (0x05) */
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struct {
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struct idpf_flex_tx_tso_ctx_qw qw0;
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struct {
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__le16 cmd_dtype;
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u8 flex[6];
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} qw1;
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} tso;
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_L2TAG2_PARSTAG_CTX (0x08) */
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struct {
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struct idpf_flex_tx_tso_ctx_qw qw0;
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struct {
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__le16 cmd_dtype;
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__le16 l2tag2;
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u8 flex0;
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u8 ptag;
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u8 flex1[2];
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} qw1;
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} tso_l2tag2_ptag;
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/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_L2TAG2_CTX (0x0B) */
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struct {
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u8 qw0_flex[8];
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struct {
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__le16 cmd_dtype;
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__le16 l2tag2;
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u8 flex[4];
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} qw1;
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} l2tag2;
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/* DTYPE = IDPF_TX_DESC_DTYPE_REINJECT_CTX (0x02) */
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struct {
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struct {
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__le32 sa_domain;
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#define IDPF_TXD_FLEX_CTX_SA_DOM_M 0xFFFF
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#define IDPF_TXD_FLEX_CTX_SA_DOM_VAL 0x10000
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__le32 sa_idx;
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#define IDPF_TXD_FLEX_CTX_SAIDX_M 0x1FFFFF
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} qw0;
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struct {
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__le16 cmd_dtype;
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__le16 txr2comp;
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#define IDPF_TXD_FLEX_CTX_TXR2COMP 0x1
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__le16 miss_txq_comp_tag;
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__le16 miss_txq_id;
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} qw1;
|
|
} reinjection_pkt;
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|
};
|
|
|
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/* Host Split Context Descriptors */
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struct idpf_flex_tx_hs_ctx_desc {
|
|
union {
|
|
struct {
|
|
__le32 host_fnum_tlen;
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|
#define IDPF_TXD_FLEX_CTX_TLEN_S 0
|
|
/* see IDPF_TXD_FLEX_CTX_TLEN_M for mask definition */
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|
#define IDPF_TXD_FLEX_CTX_FNUM_S 18
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|
#define IDPF_TXD_FLEX_CTX_FNUM_M 0x7FF
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|
#define IDPF_TXD_FLEX_CTX_HOST_S 29
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#define IDPF_TXD_FLEX_CTX_HOST_M 0x7
|
|
__le16 ftype_mss_rt;
|
|
#define IDPF_TXD_FLEX_CTX_MSS_RT_0 0
|
|
#define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF
|
|
#define IDPF_TXD_FLEX_CTX_FTYPE_S 14
|
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#define IDPF_TXD_FLEX_CTX_FTYPE_VF MAKEMASK(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S)
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#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S)
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#define IDPF_TXD_FLEX_CTX_FTYPE_PF MAKEMASK(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S)
|
|
u8 hdr_len;
|
|
u8 ptag;
|
|
} tso;
|
|
struct {
|
|
u8 flex0[2];
|
|
__le16 host_fnum_ftype;
|
|
u8 flex1[3];
|
|
u8 ptag;
|
|
} no_tso;
|
|
} qw0;
|
|
|
|
__le64 qw1_cmd_dtype;
|
|
#define IDPF_TXD_FLEX_CTX_QW1_PASID_S 16
|
|
#define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF
|
|
#define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36
|
|
#define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \
|
|
MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S)
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|
#define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37
|
|
#define IDPF_TXD_FLEX_CTX_QW1_TPH \
|
|
MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_TPH_S)
|
|
#define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38
|
|
#define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF
|
|
/* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */
|
|
#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_S 42
|
|
#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF
|
|
#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63
|
|
#define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \
|
|
MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)
|
|
/* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */
|
|
#define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48
|
|
#define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF
|
|
#define IDPF_TXD_FLEX_CTX_QW1_FLEX1_S 56
|
|
#define IDPF_TXD_FLEX_CTX_QW1_FLEX1_M 0xFF
|
|
};
|
|
#endif /* _IDPF_LAN_TXRX_H_ */
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