mirror of https://github.com/F-Stack/f-stack.git
314 lines
12 KiB
C
314 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _ROC_PLATFORM_H_
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#define _ROC_PLATFORM_H_
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#include <rte_compat.h>
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#include <rte_alarm.h>
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#include <rte_bitmap.h>
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#include <bus_pci_driver.h>
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#include <rte_byteorder.h>
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_ether.h>
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#include <rte_interrupts.h>
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#include <rte_io.h>
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#include <rte_lcore.h>
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#include <rte_log.h>
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#include <rte_malloc.h>
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#include <rte_memzone.h>
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#include <rte_pci.h>
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#include <rte_spinlock.h>
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#include <rte_string_fns.h>
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#include <rte_tailq.h>
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#include <rte_telemetry.h>
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#include "eal_filesystem.h"
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#include "roc_bits.h"
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#if defined(__ARM_FEATURE_SVE)
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#define PLT_CPU_FEATURE_PREAMBLE \
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".arch_extension crc\n" \
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".arch_extension lse\n" \
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".arch_extension sve\n"
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#else
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#define PLT_CPU_FEATURE_PREAMBLE \
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".arch_extension crc\n" \
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".arch_extension lse\n"
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#endif
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#define PLT_ASSERT RTE_ASSERT
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#define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE
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#define PLT_STD_C11 RTE_STD_C11
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#define PLT_PTR_ADD RTE_PTR_ADD
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#define PLT_PTR_SUB RTE_PTR_SUB
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#define PLT_PTR_DIFF RTE_PTR_DIFF
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#define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
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#define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
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#define PLT_MIN RTE_MIN
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#define PLT_MAX RTE_MAX
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#define PLT_DIM RTE_DIM
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#define PLT_SET_USED RTE_SET_USED
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#define PLT_SWAP RTE_SWAP
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#define PLT_STATIC_ASSERT(s) _Static_assert(s, #s)
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#define PLT_ALIGN RTE_ALIGN
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#define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL
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#define PLT_MODEL_MZ_NAME "roc_model_mz"
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#define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE
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#define BITMASK_ULL GENMASK_ULL
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#define PLT_ALIGN_CEIL RTE_ALIGN_CEIL
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#define PLT_INIT RTE_INIT
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#define PLT_MAX_ETHPORTS RTE_MAX_ETHPORTS
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#define PLT_TAILQ_FOREACH_SAFE RTE_TAILQ_FOREACH_SAFE
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#ifndef PLT_ETHER_ADDR_LEN
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#define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN
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#endif
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/* Cast to specific datatypes */
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#define PLT_PTR_CAST(val) ((void *)(val))
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#define PLT_U64_CAST(val) ((uint64_t)(val))
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#define PLT_U32_CAST(val) ((uint32_t)(val))
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#define PLT_U16_CAST(val) ((uint16_t)(val))
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/* Add / Sub pointer with scalar and cast to uint64_t */
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#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x))
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#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x))
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/** Divide ceil */
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#define PLT_DIV_CEIL(x, y) \
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({ \
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__typeof(x) __x = x; \
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__typeof(y) __y = y; \
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(__x + __y - 1) / __y; \
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})
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#define __plt_cache_aligned __rte_cache_aligned
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#define __plt_always_inline __rte_always_inline
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#define __plt_packed __rte_packed
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#define __plt_unused __rte_unused
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#define __roc_api __rte_internal
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#define plt_iova_t rte_iova_t
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#define plt_pci_addr rte_pci_addr
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#define plt_pci_device rte_pci_device
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#define plt_pci_read_config rte_pci_read_config
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#define plt_pci_find_ext_capability rte_pci_find_ext_capability
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#define plt_sysfs_value_parse eal_parse_sysfs_value
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#define plt_log2_u32 rte_log2_u32
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#define plt_cpu_to_be_16 rte_cpu_to_be_16
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#define plt_be_to_cpu_16 rte_be_to_cpu_16
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#define plt_cpu_to_be_32 rte_cpu_to_be_32
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#define plt_be_to_cpu_32 rte_be_to_cpu_32
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#define plt_cpu_to_be_64 rte_cpu_to_be_64
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#define plt_be_to_cpu_64 rte_be_to_cpu_64
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#define __plt_aligned __rte_aligned
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#define plt_align32pow2 rte_align32pow2
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#define plt_align32prevpow2 rte_align32prevpow2
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#define plt_bitmap rte_bitmap
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#define plt_bitmap_init rte_bitmap_init
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#define plt_bitmap_reset rte_bitmap_reset
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#define plt_bitmap_free rte_bitmap_free
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#define plt_bitmap_clear rte_bitmap_clear
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#define plt_bitmap_set rte_bitmap_set
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#define plt_bitmap_get rte_bitmap_get
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#define plt_bitmap_scan_init __rte_bitmap_scan_init
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#define plt_bitmap_scan rte_bitmap_scan
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#define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
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#define plt_spinlock_t rte_spinlock_t
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#define plt_spinlock_init rte_spinlock_init
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#define plt_spinlock_lock rte_spinlock_lock
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#define plt_spinlock_unlock rte_spinlock_unlock
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#define plt_spinlock_trylock rte_spinlock_trylock
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#define plt_intr_callback_register rte_intr_callback_register
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#define plt_intr_callback_unregister rte_intr_callback_unregister
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#define plt_intr_disable rte_intr_disable
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#define plt_thread_is_intr rte_thread_is_intr
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#define plt_intr_callback_fn rte_intr_callback_fn
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#define plt_ctrl_thread_create rte_ctrl_thread_create
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#define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get
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#define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set
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#define plt_intr_vec_list_index_get rte_intr_vec_list_index_get
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#define plt_intr_vec_list_index_set rte_intr_vec_list_index_set
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#define plt_intr_vec_list_alloc rte_intr_vec_list_alloc
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#define plt_intr_vec_list_free rte_intr_vec_list_free
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#define plt_intr_fd_set rte_intr_fd_set
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#define plt_intr_fd_get rte_intr_fd_get
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#define plt_intr_dev_fd_get rte_intr_dev_fd_get
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#define plt_intr_dev_fd_set rte_intr_dev_fd_set
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#define plt_intr_type_get rte_intr_type_get
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#define plt_intr_type_set rte_intr_type_set
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#define plt_intr_instance_alloc rte_intr_instance_alloc
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#define plt_intr_instance_dup rte_intr_instance_dup
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#define plt_intr_instance_free rte_intr_instance_free
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#define plt_intr_event_list_update rte_intr_event_list_update
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#define plt_intr_max_intr_get rte_intr_max_intr_get
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#define plt_intr_max_intr_set rte_intr_max_intr_set
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#define plt_intr_nb_efd_get rte_intr_nb_efd_get
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#define plt_intr_nb_efd_set rte_intr_nb_efd_set
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#define plt_intr_nb_intr_get rte_intr_nb_intr_get
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#define plt_intr_nb_intr_set rte_intr_nb_intr_set
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#define plt_intr_efds_index_get rte_intr_efds_index_get
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#define plt_intr_efds_index_set rte_intr_efds_index_set
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#define plt_intr_elist_index_get rte_intr_elist_index_get
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#define plt_intr_elist_index_set rte_intr_elist_index_set
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#define plt_alarm_set rte_eal_alarm_set
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#define plt_alarm_cancel rte_eal_alarm_cancel
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#define plt_intr_handle rte_intr_handle
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#define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align)
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#define plt_realloc rte_realloc
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#define plt_free rte_free
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#define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))
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#define plt_write64(val, addr) \
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rte_write64_relaxed((val), (volatile void *)(addr))
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#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr))
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#define plt_write32(val, addr) \
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rte_write32_relaxed((val), (volatile void *)(addr))
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#define plt_wmb() rte_wmb()
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#define plt_rmb() rte_rmb()
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#define plt_io_wmb() rte_io_wmb()
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#define plt_io_rmb() rte_io_rmb()
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#define plt_atomic_thread_fence rte_atomic_thread_fence
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#define plt_bit_relaxed_get32 rte_bit_relaxed_get32
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#define plt_bit_relaxed_set32 rte_bit_relaxed_set32
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#define plt_bit_relaxed_clear32 rte_bit_relaxed_clear32
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#define plt_bit_relaxed_get64 rte_bit_relaxed_get64
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#define plt_bit_relaxed_set64 rte_bit_relaxed_set64
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#define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64
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#define plt_mmap mmap
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#define PLT_PROT_READ PROT_READ
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#define PLT_PROT_WRITE PROT_WRITE
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#define PLT_MAP_SHARED MAP_SHARED
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#define plt_memzone rte_memzone
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#define plt_memzone_lookup rte_memzone_lookup
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#define plt_memzone_reserve_cache_align(name, sz) \
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rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE)
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#define plt_memzone_free rte_memzone_free
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#define plt_memzone_reserve_aligned(name, len, flags, align) \
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rte_memzone_reserve_aligned((name), (len), 0, (flags), (align))
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#define plt_tsc_hz rte_get_tsc_hz
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#define plt_tsc_cycles rte_get_tsc_cycles
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#define plt_delay_ms rte_delay_ms
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#define plt_delay_us rte_delay_us
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#define plt_lcore_id rte_lcore_id
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#define plt_strlcpy rte_strlcpy
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#define PLT_TEL_INT_VAL RTE_TEL_INT_VAL
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#define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL
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#define plt_tel_data rte_tel_data
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#define plt_tel_data_start_array rte_tel_data_start_array
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#define plt_tel_data_add_array_int rte_tel_data_add_array_int
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#define plt_tel_data_add_array_string rte_tel_data_add_array_string
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#define plt_tel_data_start_dict rte_tel_data_start_dict
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#define plt_tel_data_add_dict_int rte_tel_data_add_dict_int
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#define plt_tel_data_add_dict_ptr(d, n, v) \
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rte_tel_data_add_dict_u64(d, n, (uint64_t)v)
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#define plt_tel_data_add_dict_string rte_tel_data_add_dict_string
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#define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_u64
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#define plt_telemetry_register_cmd rte_telemetry_register_cmd
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/* Log */
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extern int cnxk_logtype_base;
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extern int cnxk_logtype_mbox;
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extern int cnxk_logtype_cpt;
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extern int cnxk_logtype_npa;
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extern int cnxk_logtype_nix;
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extern int cnxk_logtype_npc;
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extern int cnxk_logtype_sso;
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extern int cnxk_logtype_tim;
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extern int cnxk_logtype_tm;
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extern int cnxk_logtype_ree;
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#define plt_err(fmt, args...) \
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RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
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#define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args)
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#define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args)
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#define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args)
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#define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
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#define plt_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)
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/**
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* Log debug message if given subsystem logging is enabled.
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*/
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#define plt_dbg(subsystem, fmt, args...) \
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rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \
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"[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \
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##args)
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#define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__)
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#define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__)
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#define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__)
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#define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__)
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#define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__)
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#define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__)
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#define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__)
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#define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__)
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#define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__)
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#define plt_ree_dbg(fmt, ...) plt_dbg(ree, fmt, ##__VA_ARGS__)
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/* Datapath logs */
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#define plt_dp_err(fmt, args...) \
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RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
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#define plt_dp_info(fmt, args...) \
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RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
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#define plt_dp_dbg(fmt, args...) \
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RTE_LOG_DP(DEBUG, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
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#ifdef __cplusplus
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#define CNXK_PCI_ID(subsystem_dev, dev) \
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{ \
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RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \
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(subsystem_dev), \
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}
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#else
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#define CNXK_PCI_ID(subsystem_dev, dev) \
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{ \
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.class_id = RTE_CLASS_ANY_ID, \
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.vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \
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.subsystem_vendor_id = RTE_PCI_ANY_ID, \
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.subsystem_device_id = (subsystem_dev), \
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}
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#endif
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__rte_internal
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int roc_plt_init(void);
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/* Init callbacks */
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typedef int (*roc_plt_init_cb_t)(void);
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int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb);
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static inline const void *
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plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align)
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{
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/* To ensure returned memory is physically contiguous, bounding
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* the start and end address in 2M range.
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*/
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return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY,
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RTE_MEMZONE_IOVA_CONTIG,
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align, RTE_PGSIZE_2M);
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}
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#endif /* _ROC_PLATFORM_H_ */
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