mirror of https://github.com/F-Stack/f-stack.git
556 lines
14 KiB
C
556 lines
14 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#include <pthread.h>
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#include "roc_api.h"
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#include "roc_priv.h"
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#define CGX_CMRX_CONFIG 0x00
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#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
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#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
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#define CGX_CMRX_INT 0x40
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#define CGX_CMRX_INT_OVERFLW BIT_ULL(1)
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/*
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* CN10K stores number of lmacs in 4 bit filed
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* in contrary to CN9K which uses only 3 bits.
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*
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* In theory masks should differ yet on CN9K
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* bits beyond specified range contain zeros.
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*
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* Hence common longer mask may be used.
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*/
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#define CGX_CMRX_RX_LMACS 0x128
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#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
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#define CGX_CMRX_SCRATCH0 0x1050
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#define CGX_CMRX_SCRATCH1 0x1058
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#define CGX_MTI_MAC100X_COMMAND_CONFIG 0x8010
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#define CGX_MTI_MAC100X_COMMAND_CONFIG_RX_ENA BIT_ULL(1)
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#define CGX_MTI_MAC100X_COMMAND_CONFIG_TX_ENA BIT_ULL(0)
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static uint64_t
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roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
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{
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int shift = roc_model_is_cn10k() ? 20 : 18;
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uint64_t base = (uint64_t)roc_cgx->bar0_va;
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return plt_read64(base + (lmac << shift) + offset);
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}
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static void
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roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
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uint64_t value)
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{
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int shift = roc_model_is_cn10k() ? 20 : 18;
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uint64_t base = (uint64_t)roc_cgx->bar0_va;
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plt_write64(value, base + (lmac << shift) + offset);
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}
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static void
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roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t *scr0)
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{
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uint64_t val;
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/* clear interrupt */
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val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
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val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
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roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
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/* ack fw response */
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*scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
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roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
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}
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static int
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roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t *scr0)
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{
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int tries = 5000;
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uint64_t scr1;
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do {
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*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
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scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
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if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
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FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
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break;
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/* clear async events if any */
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
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ETH_EVT_ASYNC &&
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FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
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roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
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plt_delay_ms(1);
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} while (--tries);
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return tries ? 0 : -ETIMEDOUT;
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}
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static int
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roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t *scr0)
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{
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int tries = 5000;
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uint64_t scr1;
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do {
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*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
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scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
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if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
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FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
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break;
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plt_delay_ms(1);
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} while (--tries);
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return tries ? 0 : -ETIMEDOUT;
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}
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static int
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roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t scr1, uint64_t *scr0)
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{
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uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
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int ret;
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pthread_mutex_lock(&roc_cgx->lock);
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/* wait for ownership */
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ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
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if (ret) {
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plt_err("timed out waiting for ownership");
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goto out;
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}
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/* write command */
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scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
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roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
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/* wait for command ack */
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ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
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if (ret) {
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plt_err("timed out waiting for response");
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goto out;
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}
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if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
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goto out;
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
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plt_err("received async event instead of cmd resp event");
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ret = -EIO;
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goto out;
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}
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
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plt_err("received resp for cmd %d expected for cmd %d",
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(int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
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ret = -EIO;
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goto out;
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}
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
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plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
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roc_cgx->id, lmac,
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(int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
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ret = -EIO;
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}
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out:
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roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
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pthread_mutex_unlock(&roc_cgx->lock);
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return ret;
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}
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static unsigned int
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roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
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{
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uint64_t cgx_id;
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if (roc_model_is_cnf10kb())
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cgx_id = GENMASK_ULL(27, 24);
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else if (roc_model_is_cn10k())
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cgx_id = GENMASK_ULL(26, 24);
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else
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cgx_id = GENMASK_ULL(25, 24);
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return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
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}
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int
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roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
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{
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uint64_t val;
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int ret;
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if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
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return -EINVAL;
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ret = pthread_mutex_init(&roc_cgx->lock, NULL);
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if (ret)
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return ret;
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val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
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val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
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if (roc_model_is_cn9k())
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val = GENMASK_ULL(val - 1, 0);
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roc_cgx->lmac_bmap = val;
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roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
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return 0;
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}
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int
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roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
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{
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if (!roc_cgx)
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return -EINVAL;
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pthread_mutex_destroy(&roc_cgx->lock);
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return 0;
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}
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static bool
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roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return (lmac < MAX_LMACS_PER_CGX) &&
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(roc_cgx->lmac_bmap & BIT_ULL(lmac));
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}
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static int
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roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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bool start)
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{
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uint64_t val, reg, rx_field, tx_field;
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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if (roc_model_is_cnf10kb()) {
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reg = CGX_MTI_MAC100X_COMMAND_CONFIG;
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rx_field = CGX_MTI_MAC100X_COMMAND_CONFIG_RX_ENA;
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tx_field = CGX_MTI_MAC100X_COMMAND_CONFIG_TX_ENA;
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} else {
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reg = CGX_CMRX_CONFIG;
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rx_field = CGX_CMRX_CONFIG_DATA_PKT_RX_EN;
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tx_field = CGX_CMRX_CONFIG_DATA_PKT_TX_EN;
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}
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pthread_mutex_lock(&roc_cgx->lock);
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val = roc_bphy_cgx_read(roc_cgx, lmac, reg);
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val &= ~(rx_field | tx_field);
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if (start)
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val |= FIELD_PREP(rx_field, 1) | FIELD_PREP(tx_field, 1);
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roc_bphy_cgx_write(roc_cgx, lmac, reg, val);
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pthread_mutex_unlock(&roc_cgx->lock);
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return 0;
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}
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static int
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roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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bool enable)
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{
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uint64_t scr1, scr0;
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
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FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
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return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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}
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static int
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roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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bool enable)
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{
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uint64_t scr1, scr0;
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
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FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
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return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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}
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int
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roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
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}
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int
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roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
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}
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int
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roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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bool state)
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{
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uint64_t scr1, scr0;
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
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FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
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return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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}
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int
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roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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struct roc_bphy_cgx_link_info *info)
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{
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uint64_t scr1, scr0;
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int ret;
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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if (!info)
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return -EINVAL;
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scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
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ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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if (ret)
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return ret;
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info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
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info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
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info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
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info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
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info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
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info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
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return 0;
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}
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int
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roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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struct roc_bphy_cgx_link_mode *mode)
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{
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uint64_t scr1, scr0;
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if (roc_model_is_cn9k() &&
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(mode->use_portm_idx || mode->portm_idx || mode->mode_group_idx)) {
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return -ENOTSUP;
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}
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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if (!mode)
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return -EINVAL;
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scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX,
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mode->use_portm_idx) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX,
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mode->portm_idx) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX,
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mode->mode_group_idx) |
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FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
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return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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}
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int
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roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
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}
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int
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roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
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}
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int
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roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
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}
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int
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roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
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{
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return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
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}
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int
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roc_bphy_cgx_fec_set(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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enum roc_bphy_cgx_eth_link_fec fec)
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{
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uint64_t scr1, scr0;
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if (!roc_cgx)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_FEC) |
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FIELD_PREP(SCR1_ETH_SET_FEC_ARGS, fec);
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return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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}
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int
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roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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enum roc_bphy_cgx_eth_link_fec *fec)
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{
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uint64_t scr1, scr0;
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int ret;
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if (!roc_cgx || !fec)
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return -EINVAL;
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if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
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return -ENODEV;
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scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_SUPPORTED_FEC);
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ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
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if (ret)
|
|
return ret;
|
|
|
|
scr0 = FIELD_GET(SCR0_ETH_FEC_TYPES_S_FEC, scr0);
|
|
*fec = (enum roc_bphy_cgx_eth_link_fec)scr0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
|
|
struct roc_bphy_cgx_cpri_mode_change *mode)
|
|
{
|
|
uint64_t scr1, scr0;
|
|
|
|
if (!(roc_model_is_cnf95xxn_a0() ||
|
|
roc_model_is_cnf95xxn_a1() ||
|
|
roc_model_is_cnf95xxn_b0()))
|
|
return -ENOTSUP;
|
|
|
|
if (!roc_cgx)
|
|
return -EINVAL;
|
|
|
|
if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
|
|
return -ENODEV;
|
|
|
|
if (!mode)
|
|
return -EINVAL;
|
|
|
|
scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MODE_CHANGE) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_GSERC_IDX,
|
|
mode->gserc_idx) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_LANE_IDX, mode->lane_idx) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_RATE, mode->rate) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ,
|
|
mode->disable_leq) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE,
|
|
mode->disable_dfe);
|
|
|
|
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
|
|
}
|
|
|
|
int
|
|
roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx,
|
|
unsigned int lmac,
|
|
struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode)
|
|
{
|
|
uint64_t scr1, scr0;
|
|
|
|
if (!(roc_model_is_cnf95xxn_a0() ||
|
|
roc_model_is_cnf95xxn_a1() ||
|
|
roc_model_is_cnf95xxn_b0()))
|
|
return -ENOTSUP;
|
|
|
|
if (!roc_cgx)
|
|
return -EINVAL;
|
|
|
|
if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
|
|
return -ENODEV;
|
|
|
|
if (!mode)
|
|
return -EINVAL;
|
|
|
|
scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_TX_CONTROL) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX,
|
|
mode->gserc_idx) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX,
|
|
mode->lane_idx) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE, mode->enable);
|
|
|
|
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
|
|
}
|
|
|
|
int
|
|
roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
|
|
struct roc_bphy_cgx_cpri_mode_misc *mode)
|
|
{
|
|
uint64_t scr1, scr0;
|
|
|
|
if (!(roc_model_is_cnf95xxn_a0() ||
|
|
roc_model_is_cnf95xxn_a1() ||
|
|
roc_model_is_cnf95xxn_b0()))
|
|
return -ENOTSUP;
|
|
|
|
if (!roc_cgx)
|
|
return -EINVAL;
|
|
|
|
if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
|
|
return -ENODEV;
|
|
|
|
if (!mode)
|
|
return -EINVAL;
|
|
|
|
scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MISC) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX,
|
|
mode->gserc_idx) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX,
|
|
mode->lane_idx) |
|
|
FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_FLAGS, mode->flags);
|
|
|
|
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
|
|
}
|