mirror of https://github.com/F-Stack/f-stack.git
103 lines
3.3 KiB
ArmAsm
103 lines
3.3 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
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/*
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* Copyright (c) 2002, 2005 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ARM11 assembly functions for CPU / MMU / TLB specific operations
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*
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* XXX We make no attempt at present to take advantage of the v6 memory
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* architecture or physically tagged cache.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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/*
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* TLB functions
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*/
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ENTRY(arm11_tlb_flushID_SE)
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mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
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mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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RET
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END(arm11_tlb_flushID_SE)
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/*
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* Context switch.
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*
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* These is the CPU-specific parts of the context switcher cpu_switch()
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* These functions actually perform the TTB reload.
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*
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* NOTE: Special calling convention
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* r1, r4-r13 must be preserved
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*/
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ENTRY(arm11_context_switch)
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/*
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* We can assume that the caches will only contain kernel addresses
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* at this point. So no need to flush them again.
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*/
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
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mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
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/* Paranoia -- make sure the pipeline is empty. */
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nop
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nop
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nop
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RET
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END(arm11_context_switch)
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/*
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* TLB functions
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*/
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ENTRY(arm11_tlb_flushID)
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mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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END(arm11_tlb_flushID)
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ENTRY(arm11_tlb_flushD)
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mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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END(arm11_tlb_flushD)
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ENTRY(arm11_tlb_flushD_SE)
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mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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END(arm11_tlb_flushD_SE)
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/*
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* Other functions
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*/
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ENTRY(arm11_drain_writebuf)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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END(arm11_drain_writebuf)
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