mirror of https://github.com/F-Stack/f-stack.git
594 lines
24 KiB
C
594 lines
24 KiB
C
/*
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* Copyright 2008-2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FSL_FMAN_PORT_H
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#define __FSL_FMAN_PORT_H
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#include "fsl_fman_sp.h"
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/** @Collection Registers bit fields */
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/** @Description BMI defines */
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#define BMI_EBD_EN 0x80000000
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#define BMI_PORT_CFG_EN 0x80000000
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#define BMI_PORT_CFG_FDOVR 0x02000000
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#define BMI_PORT_CFG_IM 0x01000000
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#define BMI_PORT_STATUS_BSY 0x80000000
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#define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT
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#define BMI_DMA_ATTR_IC_STASH_ON 0x10000000
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#define BMI_DMA_ATTR_HDR_STASH_ON 0x04000000
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#define BMI_DMA_ATTR_SG_STASH_ON 0x01000000
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#define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE
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#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
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#define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000
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#define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24
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#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24
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#define BMI_RX_FRAME_END_CUT_SHIFT 16
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#define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT
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#define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT
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#define BMI_INT_BUF_MARG_SHIFT 28
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#define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT
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#define BMI_CMD_MR_LEAC 0x00200000
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#define BMI_CMD_MR_SLEAC 0x00100000
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#define BMI_CMD_MR_MA 0x00080000
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#define BMI_CMD_MR_DEAS 0x00040000
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#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \
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BMI_CMD_MR_SLEAC | \
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BMI_CMD_MR_MA | \
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BMI_CMD_MR_DEAS)
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#define BMI_CMD_TX_MR_DEF 0
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#define BMI_CMD_OP_MR_DEF (BMI_CMD_MR_DEAS | \
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BMI_CMD_MR_MA)
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#define BMI_CMD_ATTR_ORDER 0x80000000
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#define BMI_CMD_ATTR_SYNC 0x02000000
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#define BMI_CMD_ATTR_COLOR_SHIFT 26
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#define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12
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#define BMI_NEXT_ENG_FD_BITS_SHIFT 24
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#define BMI_FRAME_END_CS_IGNORE_SHIFT 24
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#define BMI_COUNTERS_EN 0x80000000
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#define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID
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#define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER
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#define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP
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#define BMI_EXT_BUF_POOL_ID_SHIFT 16
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#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
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#define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
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#define BMI_TX_FIFO_MIN_FILL_SHIFT 16
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#define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12
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#define MAX_PERFORMANCE_TASK_COMP 64
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#define MAX_PERFORMANCE_RX_QUEUE_COMP 64
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#define MAX_PERFORMANCE_TX_QUEUE_COMP 8
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#define MAX_PERFORMANCE_DMA_COMP 16
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#define MAX_PERFORMANCE_FIFO_COMP 1024
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#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24
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#define BMI_PERFORMANCE_QUEUE_COMP_SHIFT 16
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#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12
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#define BMI_RATE_LIMIT_GRAN_TX 16000 /* In Kbps */
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#define BMI_RATE_LIMIT_GRAN_OP 10000 /* In frames */
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#define BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS 1024
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#define BMI_RATE_LIMIT_MAX_BURST_SIZE 1024 /* In KBytes */
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#define BMI_RATE_LIMIT_MAX_BURST_SHIFT 16
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#define BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN 0x80000000
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#define BMI_RATE_LIMIT_SCALE_TSBS_SHIFT 16
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#define BMI_RATE_LIMIT_SCALE_EN 0x80000000
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#define BMI_SG_DISABLE FMAN_SP_SG_DISABLE
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/** @Description QMI defines */
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#define QMI_PORT_CFG_EN 0x80000000
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#define QMI_PORT_CFG_EN_COUNTERS 0x10000000
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#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000
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#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
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#define QMI_DEQ_CFG_PRI 0x80000000
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#define QMI_DEQ_CFG_TYPE1 0x10000000
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#define QMI_DEQ_CFG_TYPE2 0x20000000
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#define QMI_DEQ_CFG_TYPE3 0x30000000
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#define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000
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#define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000
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#define QMI_DEQ_CFG_SP_MASK 0xf
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#define QMI_DEQ_CFG_SP_SHIFT 20
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/** @Description General port defines */
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#define FMAN_PORT_EXT_POOLS_NUM(fm_rev_maj) \
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(((fm_rev_maj) == 4) ? 4 : 8)
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#define FMAN_PORT_MAX_EXT_POOLS_NUM 8
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#define FMAN_PORT_OBS_EXT_POOLS_NUM 2
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#define FMAN_PORT_CG_MAP_NUM 8
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#define FMAN_PORT_PRS_RESULT_WORDS_NUM 8
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#define FMAN_PORT_BMI_FIFO_UNITS 0x100
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#define FMAN_PORT_IC_OFFSET_UNITS 0x10
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/** @Collection FM Port Register Map */
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/** @Description BMI Rx port register map */
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struct fman_port_rx_bmi_regs {
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uint32_t fmbm_rcfg; /**< Rx Configuration */
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uint32_t fmbm_rst; /**< Rx Status */
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uint32_t fmbm_rda; /**< Rx DMA attributes*/
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uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
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uint32_t fmbm_rfed; /**< Rx Frame End Data*/
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uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
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uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
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uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
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uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
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uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
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uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
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uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
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uint32_t fmbm_rpp; /**< Rx Policer Profile */
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uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
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uint32_t fmbm_reth; /**< Rx Excessive Threshold */
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uint32_t reserved003c[1]; /**< (0x03C 0x03F) */
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uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
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/**< Rx Parse Results Array Init*/
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uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
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uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
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uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
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uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
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uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
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uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */
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uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */
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uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */
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uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
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/**< Buffer Manager pool Information-*/
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uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];
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/**< Allocate Counter-*/
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uint32_t reserved0130[8];
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/**< 0x130/0x140 - 0x15F reserved -*/
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uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM];
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/**< Congestion Group Map*/
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uint32_t fmbm_mpd; /**< BM Pool Depletion */
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uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */
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uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
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uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
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uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
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uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
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uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
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uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/
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uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
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uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/
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uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
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uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */
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uint32_t fmbm_rpc; /**< Rx Performance Counters*/
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uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
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uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
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uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
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uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization cntr*/
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uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
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uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
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uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
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uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */
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uint32_t fmbm_rdbg; /**< Rx Debug-*/
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};
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/** @Description BMI Tx port register map */
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struct fman_port_tx_bmi_regs {
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uint32_t fmbm_tcfg; /**< Tx Configuration */
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uint32_t fmbm_tst; /**< Tx Status */
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uint32_t fmbm_tda; /**< Tx DMA attributes */
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uint32_t fmbm_tfp; /**< Tx FIFO Parameters */
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uint32_t fmbm_tfed; /**< Tx Frame End Data */
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uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */
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uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */
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uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */
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uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */
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uint32_t fmbm_tefqid; /**< Tx Frame Error Queue ID */
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uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */
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uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */
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uint32_t fmbm_trlmt; /**< Tx Rate Limiter */
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uint32_t reserved0034[0x0e]; /**< (0x034-0x6c) */
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uint32_t fmbm_tccb; /**< Tx Coarse Classification base */
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uint32_t fmbm_tfne; /**< Tx Frame Next Engine */
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uint32_t fmbm_tpfcm[0x02]; /**< Tx Priority based Flow Control (PFC) Mapping */
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uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */
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uint32_t reserved0080[0x60]; /**< (0x080-0x200) */
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uint32_t fmbm_tstc; /**< Tx Statistics Counters */
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uint32_t fmbm_tfrc; /**< Tx Frame Counter */
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uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */
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uint32_t fmbm_tfledc; /**< Tx Frame len error discard cntr */
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uint32_t fmbm_tfufdc; /**< Tx Frame unsprt frmt discard cntr*/
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uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
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uint32_t reserved0218[0x1A]; /**< (0x218-0x280) */
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uint32_t fmbm_tpc; /**< Tx Performance Counters*/
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uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/
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uint32_t fmbm_tccn; /**< Tx Cycle Counter*/
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uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/
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uint32_t fmbm_ttcquc; /**< Tx Transmit conf Q util Counter*/
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uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/
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uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/
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};
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/** @Description BMI O/H port register map */
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struct fman_port_oh_bmi_regs {
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uint32_t fmbm_ocfg; /**< O/H Configuration */
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uint32_t fmbm_ost; /**< O/H Status */
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uint32_t fmbm_oda; /**< O/H DMA attributes */
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uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */
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uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */
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uint32_t fmbm_ofne; /**< O/H Frame Next Engine */
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uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */
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uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */
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uint32_t fmbm_opso; /**< O/H Parse Start Offset */
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uint32_t fmbm_opp; /**< O/H Policer Profile */
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uint32_t fmbm_occb; /**< O/H Coarse Classification base */
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uint32_t fmbm_oim; /**< O/H Internal margins*/
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uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/
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uint32_t fmbm_ofed; /**< O/H Frame End Data*/
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uint32_t reserved0030[2]; /**< (0x038 - 0x03F) */
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uint32_t fmbm_oprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
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/**< O/H Parse Results Array Initialization */
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uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */
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uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */
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uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */
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uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */
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uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */
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uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */
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uint32_t fmbm_orlmt; /**< O/H Rate Limiter */
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uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */
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uint32_t reserved0080[0x20]; /**< 0x080 - 0x0FF Reserved */
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uint32_t fmbm_oebmpi[2]; /**< Buf Mngr Observed Pool Info */
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uint32_t reserved0108[0x16]; /**< 0x108 - 0x15F Reserved */
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uint32_t fmbm_ocgm[FMAN_PORT_CG_MAP_NUM]; /**< Observed Congestion Group Map */
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uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */
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uint32_t reserved0184[0x1F]; /**< 0x184 - 0x1FF Reserved */
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uint32_t fmbm_ostc; /**< O/H Statistics Counters */
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uint32_t fmbm_ofrc; /**< O/H Frame Counter */
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uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */
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uint32_t fmbm_ofledc; /**< O/H Frames Len Err Discard Cntr */
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uint32_t fmbm_ofufdc; /**< O/H Frames Unsprtd Discard Cutr */
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uint32_t fmbm_offc; /**< O/H Filter Frames Counter */
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uint32_t fmbm_ofwdc; /**< Rx Frames WRED Discard Counter */
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uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Cntr */
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uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */
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uint32_t reserved0218[0x17]; /**< (0x218 - 0x27F) */
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uint32_t fmbm_opc; /**< O/H Performance Counters */
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uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */
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uint32_t fmbm_occn; /**< O/H Cycle Counter */
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uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */
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uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */
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uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */
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};
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/** @Description BMI port register map */
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union fman_port_bmi_regs {
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struct fman_port_rx_bmi_regs rx;
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struct fman_port_tx_bmi_regs tx;
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struct fman_port_oh_bmi_regs oh;
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};
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/** @Description QMI port register map */
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struct fman_port_qmi_regs {
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uint32_t fmqm_pnc; /**< PortID n Configuration Register */
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uint32_t fmqm_pns; /**< PortID n Status Register */
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uint32_t fmqm_pnts; /**< PortID n Task Status Register */
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uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */
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uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
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uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */
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uint32_t reserved024[2]; /**< 0xn024 - 0x02B */
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uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
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uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */
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uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */
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uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */
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uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
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};
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enum fman_port_dma_swap {
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E_FMAN_PORT_DMA_NO_SWAP, /**< No swap, transfer data as is */
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E_FMAN_PORT_DMA_SWAP_LE,
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/**< The transferred data should be swapped in PPC Little Endian mode */
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E_FMAN_PORT_DMA_SWAP_BE
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/**< The transferred data should be swapped in Big Endian mode */
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};
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/* Default port color */
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enum fman_port_color {
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E_FMAN_PORT_COLOR_GREEN, /**< Default port color is green */
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E_FMAN_PORT_COLOR_YELLOW, /**< Default port color is yellow */
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E_FMAN_PORT_COLOR_RED, /**< Default port color is red */
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E_FMAN_PORT_COLOR_OVERRIDE /**< Ignore color */
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};
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/* QMI dequeue from the SP channel - types */
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enum fman_port_deq_type {
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E_FMAN_PORT_DEQ_BY_PRI,
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/**< Priority precedence and Intra-Class scheduling */
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E_FMAN_PORT_DEQ_ACTIVE_FQ,
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/**< Active FQ precedence and Intra-Class scheduling */
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E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS
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/**< Active FQ precedence and override Intra-Class scheduling */
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};
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/* QMI dequeue prefetch modes */
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enum fman_port_deq_prefetch {
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E_FMAN_PORT_DEQ_NO_PREFETCH, /**< No prefetch mode */
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E_FMAN_PORT_DEQ_PART_PREFETCH, /**< Partial prefetch mode */
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E_FMAN_PORT_DEQ_FULL_PREFETCH /**< Full prefetch mode */
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};
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/* Parameters for defining performance counters behavior */
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struct fman_port_perf_cnt_params {
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uint8_t task_val; /**< Task compare value */
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uint8_t queue_val;
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/**< Rx or Tx conf queue compare value (unused for O/H ports) */
|
|
uint8_t dma_val; /**< Dma compare value */
|
|
uint32_t fifo_val; /**< Fifo compare value (in bytes) */
|
|
};
|
|
|
|
/** @Description FM Port configuration structure, used at init */
|
|
struct fman_port_cfg {
|
|
struct fman_port_perf_cnt_params perf_cnt_params;
|
|
/* BMI parameters */
|
|
enum fman_port_dma_swap dma_swap_data;
|
|
bool dma_ic_stash_on;
|
|
bool dma_header_stash_on;
|
|
bool dma_sg_stash_on;
|
|
bool dma_write_optimize;
|
|
uint16_t ic_ext_offset;
|
|
uint8_t ic_int_offset;
|
|
uint16_t ic_size;
|
|
enum fman_port_color color;
|
|
bool sync_req;
|
|
bool discard_override;
|
|
uint8_t checksum_bytes_ignore;
|
|
uint8_t rx_cut_end_bytes;
|
|
uint32_t rx_pri_elevation;
|
|
uint32_t rx_fifo_thr;
|
|
uint8_t rx_fd_bits;
|
|
uint8_t int_buf_start_margin;
|
|
uint16_t ext_buf_start_margin;
|
|
uint16_t ext_buf_end_margin;
|
|
uint32_t tx_fifo_min_level;
|
|
uint32_t tx_fifo_low_comf_level;
|
|
uint8_t tx_fifo_deq_pipeline_depth;
|
|
bool stats_counters_enable;
|
|
bool perf_counters_enable;
|
|
/* QMI parameters */
|
|
bool deq_high_pri;
|
|
enum fman_port_deq_type deq_type;
|
|
enum fman_port_deq_prefetch deq_prefetch_opt;
|
|
uint16_t deq_byte_cnt;
|
|
bool queue_counters_enable;
|
|
bool no_scatter_gather;
|
|
int errata_A006675;
|
|
int errata_A006320;
|
|
int excessive_threshold_register;
|
|
int fmbm_rebm_has_sgd;
|
|
int fmbm_tfne_has_features;
|
|
int qmi_deq_options_support;
|
|
};
|
|
|
|
enum fman_port_type {
|
|
E_FMAN_PORT_TYPE_OP = 0,
|
|
/**< Offline parsing port, shares id-s with
|
|
* host command, so must have exclusive id-s */
|
|
E_FMAN_PORT_TYPE_RX, /**< 1G Rx port */
|
|
E_FMAN_PORT_TYPE_RX_10G, /**< 10G Rx port */
|
|
E_FMAN_PORT_TYPE_TX, /**< 1G Tx port */
|
|
E_FMAN_PORT_TYPE_TX_10G, /**< 10G Tx port */
|
|
E_FMAN_PORT_TYPE_DUMMY,
|
|
E_FMAN_PORT_TYPE_HC = E_FMAN_PORT_TYPE_DUMMY
|
|
/**< Host command port, shares id-s with
|
|
* offline parsing ports, so must have exclusive id-s */
|
|
};
|
|
|
|
struct fman_port_params {
|
|
uint32_t discard_mask;
|
|
uint32_t err_mask;
|
|
uint32_t dflt_fqid;
|
|
uint32_t err_fqid;
|
|
uint8_t deq_sp;
|
|
bool dont_release_buf;
|
|
};
|
|
|
|
/* Port context - used by most API functions */
|
|
struct fman_port {
|
|
enum fman_port_type type;
|
|
uint8_t fm_rev_maj;
|
|
uint8_t fm_rev_min;
|
|
union fman_port_bmi_regs *bmi_regs;
|
|
struct fman_port_qmi_regs *qmi_regs;
|
|
bool im_en;
|
|
uint8_t ext_pools_num;
|
|
};
|
|
|
|
/** @Description External buffer pools configuration */
|
|
struct fman_port_bpools {
|
|
uint8_t count; /**< Num of pools to set up */
|
|
bool counters_enable; /**< Enable allocate counters */
|
|
uint8_t grp_bp_depleted_num;
|
|
/**< Number of depleted pools - if reached the BMI indicates
|
|
* the MAC to send a pause frame */
|
|
struct {
|
|
uint8_t bpid; /**< BM pool ID */
|
|
uint16_t size;
|
|
/**< Pool's size - must be in ascending order */
|
|
bool is_backup;
|
|
/**< If this is a backup pool */
|
|
bool grp_bp_depleted;
|
|
/**< Consider this buffer in multiple pools depletion criteria*/
|
|
bool single_bp_depleted;
|
|
/**< Consider this buffer in single pool depletion criteria */
|
|
bool pfc_priorities_en;
|
|
} bpool[FMAN_PORT_MAX_EXT_POOLS_NUM];
|
|
};
|
|
|
|
enum fman_port_rate_limiter_scale_down {
|
|
E_FMAN_PORT_RATE_DOWN_NONE,
|
|
E_FMAN_PORT_RATE_DOWN_BY_2,
|
|
E_FMAN_PORT_RATE_DOWN_BY_4,
|
|
E_FMAN_PORT_RATE_DOWN_BY_8
|
|
};
|
|
|
|
/* Rate limiter configuration */
|
|
struct fman_port_rate_limiter {
|
|
uint8_t count_1micro_bit;
|
|
bool high_burst_size_gran;
|
|
/**< Defines burst_size granularity for OP ports; when TRUE,
|
|
* burst_size below counts in frames, otherwise in 10^3 frames */
|
|
uint16_t burst_size;
|
|
/**< Max burst size, in KBytes for Tx port, according to
|
|
* high_burst_size_gran definition for OP port */
|
|
uint32_t rate;
|
|
/**< In Kbps for Tx port, in frames/sec for OP port */
|
|
enum fman_port_rate_limiter_scale_down rate_factor;
|
|
};
|
|
|
|
/* BMI statistics counters */
|
|
enum fman_port_stats_counters {
|
|
E_FMAN_PORT_STATS_CNT_FRAME,
|
|
/**< Number of processed frames; valid for all ports */
|
|
E_FMAN_PORT_STATS_CNT_DISCARD,
|
|
/**< For Rx ports - frames discarded by QMAN, for Tx or O/H ports -
|
|
* frames discarded due to DMA error; valid for all ports */
|
|
E_FMAN_PORT_STATS_CNT_DEALLOC_BUF,
|
|
/**< Number of buffer deallocate operations; valid for all ports */
|
|
E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME,
|
|
/**< Number of bad Rx frames, like CRC error, Rx FIFO overflow etc;
|
|
* valid for Rx ports only */
|
|
E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME,
|
|
/**< Number of Rx oversized frames, that is frames exceeding max frame
|
|
* size configured for the corresponding ETH controller;
|
|
* valid for Rx ports only */
|
|
E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF,
|
|
/**< Frames discarded due to lack of external buffers; valid for
|
|
* Rx ports only */
|
|
E_FMAN_PORT_STATS_CNT_LEN_ERR,
|
|
/**< Frames discarded due to frame length error; valid for Tx and
|
|
* O/H ports only */
|
|
E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT,
|
|
/**< Frames discarded due to unsupported FD format; valid for Tx
|
|
* and O/H ports only */
|
|
E_FMAN_PORT_STATS_CNT_FILTERED_FRAME,
|
|
/**< Number of frames filtered out by PCD module; valid for
|
|
* Rx and OP ports only */
|
|
E_FMAN_PORT_STATS_CNT_DMA_ERR,
|
|
/**< Frames rejected by QMAN that were not able to release their
|
|
* buffers due to DMA error; valid for Rx and O/H ports only */
|
|
E_FMAN_PORT_STATS_CNT_WRED_DISCARD
|
|
/**< Frames going through O/H port that were not able to to enter the
|
|
* return queue due to WRED algorithm; valid for O/H ports only */
|
|
};
|
|
|
|
/* BMI performance counters */
|
|
enum fman_port_perf_counters {
|
|
E_FMAN_PORT_PERF_CNT_CYCLE, /**< Cycle counter */
|
|
E_FMAN_PORT_PERF_CNT_TASK_UTIL, /**< Tasks utilization counter */
|
|
E_FMAN_PORT_PERF_CNT_QUEUE_UTIL,
|
|
/**< For Rx ports - Rx queue utilization, for Tx ports - Tx conf queue
|
|
* utilization; not valid for O/H ports */
|
|
E_FMAN_PORT_PERF_CNT_DMA_UTIL, /**< DMA utilization counter */
|
|
E_FMAN_PORT_PERF_CNT_FIFO_UTIL, /**< FIFO utilization counter */
|
|
E_FMAN_PORT_PERF_CNT_RX_PAUSE
|
|
/**< Number of cycles in which Rx pause activation control is on;
|
|
* valid for Rx ports only */
|
|
};
|
|
|
|
/* QMI counters */
|
|
enum fman_port_qmi_counters {
|
|
E_FMAN_PORT_ENQ_TOTAL, /**< EnQ tot frame cntr */
|
|
E_FMAN_PORT_DEQ_TOTAL, /**< DeQ tot frame cntr; invalid for Rx ports */
|
|
E_FMAN_PORT_DEQ_FROM_DFLT,
|
|
/**< Dequeue from default FQID counter not valid for Rx ports */
|
|
E_FMAN_PORT_DEQ_CONFIRM /**< DeQ confirm cntr invalid for Rx ports */
|
|
};
|
|
|
|
|
|
/** @Collection FM Port API */
|
|
void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type);
|
|
int fman_port_init(struct fman_port *port,
|
|
struct fman_port_cfg *cfg,
|
|
struct fman_port_params *params);
|
|
int fman_port_enable(struct fman_port *port);
|
|
int fman_port_disable(const struct fman_port *port);
|
|
int fman_port_set_bpools(const struct fman_port *port,
|
|
const struct fman_port_bpools *bp);
|
|
int fman_port_set_rate_limiter(struct fman_port *port,
|
|
struct fman_port_rate_limiter *rate_limiter);
|
|
int fman_port_delete_rate_limiter(struct fman_port *port);
|
|
int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask);
|
|
int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask);
|
|
int fman_port_modify_rx_fd_bits(struct fman_port *port,
|
|
uint8_t rx_fd_bits,
|
|
bool add);
|
|
int fman_port_set_perf_cnt_params(struct fman_port *port,
|
|
struct fman_port_perf_cnt_params *params);
|
|
int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable);
|
|
int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable);
|
|
int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable);
|
|
int fman_port_set_bpool_cnt_mode(struct fman_port *port,
|
|
uint8_t bpid,
|
|
bool enable);
|
|
uint32_t fman_port_get_stats_counter(struct fman_port *port,
|
|
enum fman_port_stats_counters counter);
|
|
void fman_port_set_stats_counter(struct fman_port *port,
|
|
enum fman_port_stats_counters counter,
|
|
uint32_t value);
|
|
uint32_t fman_port_get_perf_counter(struct fman_port *port,
|
|
enum fman_port_perf_counters counter);
|
|
void fman_port_set_perf_counter(struct fman_port *port,
|
|
enum fman_port_perf_counters counter,
|
|
uint32_t value);
|
|
uint32_t fman_port_get_qmi_counter(struct fman_port *port,
|
|
enum fman_port_qmi_counters counter);
|
|
void fman_port_set_qmi_counter(struct fman_port *port,
|
|
enum fman_port_qmi_counters counter,
|
|
uint32_t value);
|
|
uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid);
|
|
void fman_port_set_bpool_counter(struct fman_port *port,
|
|
uint8_t bpid,
|
|
uint32_t value);
|
|
int fman_port_add_congestion_grps(struct fman_port *port,
|
|
uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]);
|
|
int fman_port_remove_congestion_grps(struct fman_port *port,
|
|
uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]);
|
|
|
|
|
|
#endif /* __FSL_FMAN_PORT_H */
|