mirror of https://github.com/F-Stack/f-stack.git
822 lines
19 KiB
C
822 lines
19 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2018 Intel Corporation
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*/
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#include "opae_hw_api.h"
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#include "ifpga_api.h"
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#include "ifpga_hw.h"
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#include "ifpga_enumerate.h"
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#include "ifpga_feature_dev.h"
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struct build_feature_devs_info {
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struct opae_adapter_data_pci *pci_data;
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struct ifpga_afu_info *acc_info;
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void *fiu;
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enum fpga_id_type current_type;
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int current_port_id;
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void *ioaddr;
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void *ioend;
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uint64_t phys_addr;
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int current_bar;
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void *pfme_hdr;
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struct ifpga_hw *hw;
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};
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struct feature_info {
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const char *name;
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u32 resource_size;
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int feature_index;
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int revision_id;
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unsigned int vec_start;
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unsigned int vec_cnt;
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struct feature_ops *ops;
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};
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/* indexed by fme feature IDs which are defined in 'enum fme_feature_id'. */
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static struct feature_info fme_features[] = {
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{
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.name = FME_FEATURE_HEADER,
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.resource_size = sizeof(struct feature_fme_header),
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.feature_index = FME_FEATURE_ID_HEADER,
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.revision_id = FME_HEADER_REVISION,
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.ops = &fme_hdr_ops,
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},
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{
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.name = FME_FEATURE_THERMAL_MGMT,
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.resource_size = sizeof(struct feature_fme_thermal),
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.feature_index = FME_FEATURE_ID_THERMAL_MGMT,
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.revision_id = FME_THERMAL_MGMT_REVISION,
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.ops = &fme_thermal_mgmt_ops,
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},
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{
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.name = FME_FEATURE_POWER_MGMT,
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.resource_size = sizeof(struct feature_fme_power),
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.feature_index = FME_FEATURE_ID_POWER_MGMT,
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.revision_id = FME_POWER_MGMT_REVISION,
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.ops = &fme_power_mgmt_ops,
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},
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{
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.name = FME_FEATURE_GLOBAL_IPERF,
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.resource_size = sizeof(struct feature_fme_iperf),
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.feature_index = FME_FEATURE_ID_GLOBAL_IPERF,
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.revision_id = FME_GLOBAL_IPERF_REVISION,
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.ops = &fme_global_iperf_ops,
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},
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{
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.name = FME_FEATURE_GLOBAL_ERR,
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.resource_size = sizeof(struct feature_fme_err),
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.feature_index = FME_FEATURE_ID_GLOBAL_ERR,
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.revision_id = FME_GLOBAL_ERR_REVISION,
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.ops = &fme_global_err_ops,
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},
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{
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.name = FME_FEATURE_PR_MGMT,
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.resource_size = sizeof(struct feature_fme_pr),
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.feature_index = FME_FEATURE_ID_PR_MGMT,
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.revision_id = FME_PR_MGMT_REVISION,
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.ops = &fme_pr_mgmt_ops,
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},
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{
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.name = FME_FEATURE_HSSI_ETH,
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.resource_size = sizeof(struct feature_fme_hssi),
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.feature_index = FME_FEATURE_ID_HSSI_ETH,
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.revision_id = FME_HSSI_ETH_REVISION
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},
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{
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.name = FME_FEATURE_GLOBAL_DPERF,
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.resource_size = sizeof(struct feature_fme_dperf),
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.feature_index = FME_FEATURE_ID_GLOBAL_DPERF,
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.revision_id = FME_GLOBAL_DPERF_REVISION,
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.ops = &fme_global_dperf_ops,
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}
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};
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static struct feature_info port_features[] = {
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{
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.name = PORT_FEATURE_HEADER,
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.resource_size = sizeof(struct feature_port_header),
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.feature_index = PORT_FEATURE_ID_HEADER,
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.revision_id = PORT_HEADER_REVISION,
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.ops = &ifpga_rawdev_port_hdr_ops,
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},
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{
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.name = PORT_FEATURE_ERR,
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.resource_size = sizeof(struct feature_port_error),
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.feature_index = PORT_FEATURE_ID_ERROR,
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.revision_id = PORT_ERR_REVISION,
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.ops = &ifpga_rawdev_port_error_ops,
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},
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{
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.name = PORT_FEATURE_UMSG,
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.resource_size = sizeof(struct feature_port_umsg),
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.feature_index = PORT_FEATURE_ID_UMSG,
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.revision_id = PORT_UMSG_REVISION,
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},
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{
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.name = PORT_FEATURE_UINT,
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.resource_size = sizeof(struct feature_port_uint),
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.feature_index = PORT_FEATURE_ID_UINT,
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.revision_id = PORT_UINT_REVISION,
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.ops = &ifpga_rawdev_port_uint_ops,
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},
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{
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.name = PORT_FEATURE_STP,
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.resource_size = PORT_FEATURE_STP_REGION_SIZE,
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.feature_index = PORT_FEATURE_ID_STP,
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.revision_id = PORT_STP_REVISION,
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.ops = &ifpga_rawdev_port_stp_ops,
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},
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{
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.name = PORT_FEATURE_UAFU,
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/* UAFU feature size should be read from PORT_CAP.MMIOSIZE.
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* Will set uafu feature size while parse port device.
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*/
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.resource_size = 0,
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.feature_index = PORT_FEATURE_ID_UAFU,
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.revision_id = PORT_UAFU_REVISION
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},
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};
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static u64 feature_id(void __iomem *start)
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{
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struct feature_header header;
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header.csr = readq(start);
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switch (header.type) {
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case FEATURE_TYPE_FIU:
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return FEATURE_ID_HEADER;
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case FEATURE_TYPE_PRIVATE:
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return header.id;
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case FEATURE_TYPE_AFU:
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return FEATURE_ID_AFU;
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}
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WARN_ON(1);
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return 0;
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}
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static int
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build_info_add_sub_feature(struct build_feature_devs_info *binfo,
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struct feature_info *finfo, void __iomem *start)
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{
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struct ifpga_hw *hw = binfo->hw;
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struct feature *feature = NULL;
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int feature_idx = finfo->feature_index;
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unsigned int vec_start = finfo->vec_start;
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unsigned int vec_cnt = finfo->vec_cnt;
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struct feature_irq_ctx *ctx = NULL;
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int port_id, ret = 0;
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unsigned int i;
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if (binfo->current_type == FME_ID) {
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feature = &hw->fme.sub_feature[feature_idx];
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feature->parent = &hw->fme;
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} else if (binfo->current_type == PORT_ID) {
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port_id = binfo->current_port_id;
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feature = &hw->port[port_id].sub_feature[feature_idx];
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feature->parent = &hw->port[port_id];
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} else {
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return -EFAULT;
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}
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feature->state = IFPGA_FEATURE_ATTACHED;
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feature->addr = start;
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feature->id = feature_id(start);
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feature->size = finfo->resource_size;
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feature->name = finfo->name;
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feature->revision = finfo->revision_id;
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feature->ops = finfo->ops;
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feature->phys_addr = binfo->phys_addr +
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((u8 *)start - (u8 *)binfo->ioaddr);
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if (vec_cnt) {
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if (vec_start + vec_cnt <= vec_start)
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return -EINVAL;
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ctx = zmalloc(sizeof(*ctx) * vec_cnt);
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if (!ctx)
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return -ENOMEM;
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for (i = 0; i < vec_cnt; i++) {
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ctx[i].eventfd = -1;
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ctx[i].idx = vec_start + i;
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}
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}
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feature->ctx = ctx;
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feature->ctx_num = vec_cnt;
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feature->vfio_dev_fd = binfo->pci_data->vfio_dev_fd;
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return ret;
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}
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static int
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create_feature_instance(struct build_feature_devs_info *binfo,
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void __iomem *start, struct feature_info *finfo)
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{
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struct feature_header *hdr = start;
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if (finfo->revision_id != SKIP_REVISION_CHECK &&
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hdr->revision > finfo->revision_id) {
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dev_err(binfo, "feature %s revision :default:%x, now at:%x, mis-match.\n",
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finfo->name, finfo->revision_id, hdr->revision);
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}
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return build_info_add_sub_feature(binfo, finfo, start);
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}
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/*
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* UAFU GUID is dynamic as it can be changed after FME downloads different
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* Green Bitstream to the port, so we treat the unknown GUIDs which are
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* attached on port's feature list as UAFU.
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*/
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static bool feature_is_UAFU(struct build_feature_devs_info *binfo)
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{
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if (binfo->current_type != PORT_ID)
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return false;
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return true;
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}
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static int parse_feature_port_uafu(struct build_feature_devs_info *binfo,
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struct feature_header *hdr)
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{
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enum port_feature_id id = PORT_FEATURE_ID_UAFU;
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struct ifpga_afu_info *info;
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void *start = (void *)hdr;
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int ret;
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if (port_features[id].resource_size) {
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ret = create_feature_instance(binfo, hdr, &port_features[id]);
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} else {
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dev_err(binfo, "the uafu feature header is mis-configured.\n");
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ret = -EINVAL;
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}
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if (ret)
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return ret;
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/* FIXME: need to figure out a better name */
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info = malloc(sizeof(*info));
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if (!info)
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return -ENOMEM;
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info->region[0].addr = start;
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info->region[0].phys_addr = binfo->phys_addr +
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(uint8_t *)start - (uint8_t *)binfo->ioaddr;
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info->region[0].len = port_features[id].resource_size;
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port_features[id].resource_size = 0;
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info->num_regions = 1;
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binfo->acc_info = info;
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return ret;
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}
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static int parse_feature_afus(struct build_feature_devs_info *binfo,
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struct feature_header *hdr)
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{
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int ret;
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struct feature_afu_header *afu_hdr, header;
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u8 __iomem *start;
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u8 __iomem *end = binfo->ioend;
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start = (u8 __iomem *)hdr;
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for (; start < end; start += header.next_afu) {
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if ((unsigned int)(end - start) <
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(unsigned int)(sizeof(*afu_hdr) + sizeof(*hdr)))
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return -EINVAL;
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hdr = (struct feature_header *)start;
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afu_hdr = (struct feature_afu_header *)(hdr + 1);
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header.csr = readq(&afu_hdr->csr);
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if (feature_is_UAFU(binfo)) {
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ret = parse_feature_port_uafu(binfo, hdr);
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if (ret)
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return ret;
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}
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if (!header.next_afu)
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break;
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}
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return 0;
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}
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/* create and register proper private data */
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static int build_info_commit_dev(struct build_feature_devs_info *binfo)
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{
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struct ifpga_afu_info *info = binfo->acc_info;
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struct ifpga_hw *hw = binfo->hw;
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struct opae_manager *mgr;
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struct opae_bridge *br;
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struct opae_accelerator *acc;
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if (!binfo->fiu)
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return 0;
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if (binfo->current_type == PORT_ID) {
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/* return error if no valid acc info data structure */
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if (!info)
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return -EFAULT;
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br = opae_bridge_alloc(hw->adapter->name, &ifpga_br_ops,
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binfo->fiu);
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if (!br)
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return -ENOMEM;
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br->id = binfo->current_port_id;
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/* update irq info */
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info->num_irqs = port_features[PORT_FEATURE_ID_UINT].vec_cnt;
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acc = opae_accelerator_alloc(hw->adapter->name,
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&ifpga_acc_ops, info);
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if (!acc) {
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opae_bridge_free(br);
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return -ENOMEM;
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}
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acc->br = br;
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acc->index = br->id;
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opae_adapter_add_acc(hw->adapter, acc);
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} else if (binfo->current_type == FME_ID) {
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mgr = opae_manager_alloc(hw->adapter->name, &ifpga_mgr_ops,
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binfo->fiu);
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if (!mgr)
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return -ENOMEM;
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mgr->adapter = hw->adapter;
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hw->adapter->mgr = mgr;
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}
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binfo->fiu = NULL;
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return 0;
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}
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static int
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build_info_create_dev(struct build_feature_devs_info *binfo,
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enum fpga_id_type type, unsigned int index)
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{
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int ret;
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ret = build_info_commit_dev(binfo);
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if (ret)
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return ret;
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binfo->current_type = type;
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if (type == FME_ID) {
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binfo->fiu = &binfo->hw->fme;
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} else if (type == PORT_ID) {
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binfo->fiu = &binfo->hw->port[index];
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binfo->current_port_id = index;
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}
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return 0;
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}
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static int parse_feature_fme(struct build_feature_devs_info *binfo,
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struct feature_header *start)
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{
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struct ifpga_hw *hw = binfo->hw;
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struct ifpga_fme_hw *fme = &hw->fme;
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int ret;
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ret = build_info_create_dev(binfo, FME_ID, 0);
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if (ret)
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return ret;
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/* Update FME states */
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fme->state = IFPGA_FME_IMPLEMENTED;
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fme->parent = hw;
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spinlock_init(&fme->lock);
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return create_feature_instance(binfo, start,
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&fme_features[FME_FEATURE_ID_HEADER]);
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}
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static int parse_feature_port(struct build_feature_devs_info *binfo,
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void __iomem *start)
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{
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struct feature_port_header *port_hdr;
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struct feature_port_capability capability;
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struct ifpga_hw *hw = binfo->hw;
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struct ifpga_port_hw *port;
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unsigned int port_id;
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int ret;
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/* Get current port's id */
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port_hdr = (struct feature_port_header *)start;
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capability.csr = readq(&port_hdr->capability);
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port_id = capability.port_number;
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ret = build_info_create_dev(binfo, PORT_ID, port_id);
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if (ret)
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return ret;
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/*found a Port device*/
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port = &hw->port[port_id];
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port->port_id = binfo->current_port_id;
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port->parent = hw;
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port->state = IFPGA_PORT_ATTACHED;
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spinlock_init(&port->lock);
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return create_feature_instance(binfo, start,
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&port_features[PORT_FEATURE_ID_HEADER]);
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}
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static void enable_port_uafu(struct build_feature_devs_info *binfo,
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void __iomem *start)
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{
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enum port_feature_id id = PORT_FEATURE_ID_UAFU;
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struct feature_port_header *port_hdr;
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struct feature_port_capability capability;
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struct ifpga_port_hw *port = &binfo->hw->port[binfo->current_port_id];
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port_hdr = (struct feature_port_header *)start;
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capability.csr = readq(&port_hdr->capability);
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port_features[id].resource_size = (capability.mmio_size << 10);
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/*
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* From spec, to Enable UAFU, we should reset related port,
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* or the whole mmio space in this UAFU will be invalid
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*/
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if (port_features[id].resource_size)
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fpga_port_reset(port);
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}
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static int parse_feature_fiu(struct build_feature_devs_info *binfo,
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struct feature_header *hdr)
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{
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struct feature_header header;
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struct feature_fiu_header *fiu_hdr, fiu_header;
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u8 __iomem *start = (u8 __iomem *)hdr;
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int ret;
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header.csr = readq(hdr);
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switch (header.id) {
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case FEATURE_FIU_ID_FME:
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ret = parse_feature_fme(binfo, hdr);
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binfo->pfme_hdr = hdr;
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if (ret)
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return ret;
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break;
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case FEATURE_FIU_ID_PORT:
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ret = parse_feature_port(binfo, hdr);
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enable_port_uafu(binfo, hdr);
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if (ret)
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return ret;
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/* Check Port FIU's next_afu pointer to User AFU DFH */
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fiu_hdr = (struct feature_fiu_header *)(hdr + 1);
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fiu_header.csr = readq(&fiu_hdr->csr);
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if (fiu_header.next_afu) {
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start += fiu_header.next_afu;
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ret = parse_feature_afus(binfo,
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(struct feature_header *)start);
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if (ret)
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return ret;
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} else {
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dev_info(binfo, "No AFUs detected on Port\n");
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}
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break;
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default:
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dev_info(binfo, "FIU TYPE %d is not supported yet.\n",
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header.id);
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}
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return 0;
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}
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static void parse_feature_irqs(struct build_feature_devs_info *binfo,
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void __iomem *start, struct feature_info *finfo)
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{
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finfo->vec_start = 0;
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finfo->vec_cnt = 0;
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|
|
UNUSED(binfo);
|
|
|
|
if (!strcmp(finfo->name, PORT_FEATURE_UINT)) {
|
|
struct feature_port_uint *port_uint = start;
|
|
struct feature_port_uint_cap uint_cap;
|
|
|
|
uint_cap.csr = readq(&port_uint->capability);
|
|
if (uint_cap.intr_num) {
|
|
finfo->vec_start = uint_cap.first_vec_num;
|
|
finfo->vec_cnt = uint_cap.intr_num;
|
|
} else {
|
|
dev_debug(binfo, "UAFU doesn't support interrupt\n");
|
|
}
|
|
} else if (!strcmp(finfo->name, PORT_FEATURE_ERR)) {
|
|
struct feature_port_error *port_err = start;
|
|
struct feature_port_err_capability port_err_cap;
|
|
|
|
port_err_cap.csr = readq(&port_err->error_capability);
|
|
if (port_err_cap.support_intr) {
|
|
finfo->vec_start = port_err_cap.intr_vector_num;
|
|
finfo->vec_cnt = 1;
|
|
} else {
|
|
dev_debug(&binfo, "Port error doesn't support interrupt\n");
|
|
}
|
|
|
|
} else if (!strcmp(finfo->name, FME_FEATURE_GLOBAL_ERR)) {
|
|
struct feature_fme_err *fme_err = start;
|
|
struct feature_fme_error_capability fme_err_cap;
|
|
|
|
fme_err_cap.csr = readq(&fme_err->fme_err_capability);
|
|
if (fme_err_cap.support_intr) {
|
|
finfo->vec_start = fme_err_cap.intr_vector_num;
|
|
finfo->vec_cnt = 1;
|
|
} else {
|
|
dev_debug(&binfo, "FME error doesn't support interrupt\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
static int parse_feature_fme_private(struct build_feature_devs_info *binfo,
|
|
struct feature_header *hdr)
|
|
{
|
|
struct feature_header header;
|
|
|
|
header.csr = readq(hdr);
|
|
|
|
if (header.id >= ARRAY_SIZE(fme_features)) {
|
|
dev_err(binfo, "FME feature id %x is not supported yet.\n",
|
|
header.id);
|
|
return 0;
|
|
}
|
|
|
|
parse_feature_irqs(binfo, hdr, &fme_features[header.id]);
|
|
|
|
return create_feature_instance(binfo, hdr, &fme_features[header.id]);
|
|
}
|
|
|
|
static int parse_feature_port_private(struct build_feature_devs_info *binfo,
|
|
struct feature_header *hdr)
|
|
{
|
|
struct feature_header header;
|
|
enum port_feature_id id;
|
|
|
|
header.csr = readq(hdr);
|
|
/*
|
|
* the region of port feature id is [0x10, 0x13], + 1 to reserve 0
|
|
* which is dedicated for port-hdr.
|
|
*/
|
|
id = (header.id & 0x000f) + 1;
|
|
|
|
if (id >= ARRAY_SIZE(port_features)) {
|
|
dev_err(binfo, "Port feature id %x is not supported yet.\n",
|
|
header.id);
|
|
return 0;
|
|
}
|
|
|
|
parse_feature_irqs(binfo, hdr, &port_features[id]);
|
|
|
|
return create_feature_instance(binfo, hdr, &port_features[id]);
|
|
}
|
|
|
|
static int parse_feature_private(struct build_feature_devs_info *binfo,
|
|
struct feature_header *hdr)
|
|
{
|
|
struct feature_header header;
|
|
|
|
header.csr = readq(hdr);
|
|
|
|
switch (binfo->current_type) {
|
|
case FME_ID:
|
|
return parse_feature_fme_private(binfo, hdr);
|
|
case PORT_ID:
|
|
return parse_feature_port_private(binfo, hdr);
|
|
default:
|
|
dev_err(binfo, "private feature %x belonging to AFU %d (unknown_type) is not supported yet.\n",
|
|
header.id, binfo->current_type);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int parse_feature(struct build_feature_devs_info *binfo,
|
|
struct feature_header *hdr)
|
|
{
|
|
struct feature_header header;
|
|
int ret = 0;
|
|
|
|
header.csr = readq(hdr);
|
|
|
|
switch (header.type) {
|
|
case FEATURE_TYPE_AFU:
|
|
ret = parse_feature_afus(binfo, hdr);
|
|
break;
|
|
case FEATURE_TYPE_PRIVATE:
|
|
ret = parse_feature_private(binfo, hdr);
|
|
break;
|
|
case FEATURE_TYPE_FIU:
|
|
ret = parse_feature_fiu(binfo, hdr);
|
|
break;
|
|
default:
|
|
dev_err(binfo, "Feature Type %x is not supported.\n",
|
|
hdr->type);
|
|
};
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
parse_feature_list(struct build_feature_devs_info *binfo, u8 __iomem *start)
|
|
{
|
|
struct feature_header *hdr, header;
|
|
u8 __iomem *end = (u8 __iomem *)binfo->ioend;
|
|
int ret = 0;
|
|
|
|
for (; start < end; start += header.next_header_offset) {
|
|
if ((unsigned int)(end - start) < (unsigned int)sizeof(*hdr)) {
|
|
dev_err(binfo, "The region is too small to contain a feature.\n");
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
hdr = (struct feature_header *)start;
|
|
ret = parse_feature(binfo, hdr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
header.csr = readq(hdr);
|
|
if (!header.next_header_offset)
|
|
break;
|
|
}
|
|
|
|
return build_info_commit_dev(binfo);
|
|
}
|
|
|
|
/* switch the memory mapping to BAR# @bar */
|
|
static int parse_switch_to(struct build_feature_devs_info *binfo, int bar)
|
|
{
|
|
struct opae_adapter_data_pci *pci_data = binfo->pci_data;
|
|
|
|
if (!pci_data->region[bar].addr)
|
|
return -ENOMEM;
|
|
|
|
binfo->ioaddr = pci_data->region[bar].addr;
|
|
binfo->ioend = (u8 __iomem *)binfo->ioaddr + pci_data->region[bar].len;
|
|
binfo->phys_addr = pci_data->region[bar].phys_addr;
|
|
binfo->current_bar = bar;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int parse_ports_from_fme(struct build_feature_devs_info *binfo)
|
|
{
|
|
struct feature_fme_header *fme_hdr;
|
|
struct feature_fme_port port;
|
|
int i = 0, ret = 0;
|
|
|
|
if (!binfo->pfme_hdr) {
|
|
dev_info(binfo, "VF is detected.\n");
|
|
return ret;
|
|
}
|
|
|
|
fme_hdr = binfo->pfme_hdr;
|
|
|
|
do {
|
|
port.csr = readq(&fme_hdr->port[i]);
|
|
if (!port.port_implemented)
|
|
break;
|
|
|
|
/* skip port which only could be accessed via VF */
|
|
if (port.afu_access_control == FME_AFU_ACCESS_VF)
|
|
continue;
|
|
|
|
ret = parse_switch_to(binfo, port.port_bar);
|
|
if (ret)
|
|
break;
|
|
|
|
ret = parse_feature_list(binfo,
|
|
(u8 __iomem *)binfo->ioaddr +
|
|
port.port_offset);
|
|
if (ret)
|
|
break;
|
|
} while (++i < MAX_FPGA_PORT_NUM);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct build_feature_devs_info *
|
|
build_info_alloc_and_init(struct ifpga_hw *hw)
|
|
{
|
|
struct build_feature_devs_info *binfo;
|
|
|
|
binfo = zmalloc(sizeof(*binfo));
|
|
if (!binfo)
|
|
return binfo;
|
|
|
|
binfo->hw = hw;
|
|
binfo->pci_data = hw->pci_data;
|
|
|
|
/* fpga feature list starts from BAR 0 */
|
|
if (parse_switch_to(binfo, 0)) {
|
|
free(binfo);
|
|
return NULL;
|
|
}
|
|
|
|
return binfo;
|
|
}
|
|
|
|
static void build_info_free(struct build_feature_devs_info *binfo)
|
|
{
|
|
free(binfo);
|
|
}
|
|
|
|
static void ifpga_print_device_feature_list(struct ifpga_hw *hw)
|
|
{
|
|
struct ifpga_fme_hw *fme = &hw->fme;
|
|
struct ifpga_port_hw *port;
|
|
struct feature *feature;
|
|
int i, j;
|
|
|
|
dev_info(hw, "found fme_device, is in PF: %s\n",
|
|
is_ifpga_hw_pf(hw) ? "yes" : "no");
|
|
|
|
for (i = 0; i < FME_FEATURE_ID_MAX; i++) {
|
|
feature = &fme->sub_feature[i];
|
|
if (feature->state != IFPGA_FEATURE_ATTACHED)
|
|
continue;
|
|
|
|
dev_info(hw, "%12s: 0x%p - 0x%p - paddr: 0x%lx\n",
|
|
feature->name, feature->addr,
|
|
feature->addr + feature->size - 1,
|
|
(unsigned long)feature->phys_addr);
|
|
}
|
|
|
|
for (i = 0; i < MAX_FPGA_PORT_NUM; i++) {
|
|
port = &hw->port[i];
|
|
|
|
if (port->state != IFPGA_PORT_ATTACHED)
|
|
continue;
|
|
|
|
dev_info(hw, "port device: %d\n", port->port_id);
|
|
|
|
for (j = 0; j < PORT_FEATURE_ID_MAX; j++) {
|
|
feature = &port->sub_feature[j];
|
|
if (feature->state != IFPGA_FEATURE_ATTACHED)
|
|
continue;
|
|
|
|
dev_info(hw, "%12s: 0x%p - 0x%p - paddr:0x%lx\n",
|
|
feature->name,
|
|
feature->addr,
|
|
feature->addr +
|
|
feature->size - 1,
|
|
(unsigned long)feature->phys_addr);
|
|
}
|
|
}
|
|
}
|
|
|
|
int ifpga_bus_enumerate(struct ifpga_hw *hw)
|
|
{
|
|
struct build_feature_devs_info *binfo;
|
|
int ret;
|
|
|
|
binfo = build_info_alloc_and_init(hw);
|
|
if (!binfo)
|
|
return -ENOMEM;
|
|
|
|
ret = parse_feature_list(binfo, binfo->ioaddr);
|
|
if (ret)
|
|
goto exit;
|
|
|
|
ret = parse_ports_from_fme(binfo);
|
|
if (ret)
|
|
goto exit;
|
|
|
|
ifpga_print_device_feature_list(hw);
|
|
|
|
exit:
|
|
build_info_free(binfo);
|
|
return ret;
|
|
}
|
|
|
|
int ifpga_bus_init(struct ifpga_hw *hw)
|
|
{
|
|
int i;
|
|
|
|
fme_hw_init(&hw->fme);
|
|
for (i = 0; i < MAX_FPGA_PORT_NUM; i++)
|
|
port_hw_init(&hw->port[i]);
|
|
|
|
return 0;
|
|
}
|