mirror of https://github.com/F-Stack/f-stack.git
80 lines
3.1 KiB
C
80 lines
3.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_INTR_H_
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#define _HNS3_INTR_H_
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#define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
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#define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
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#define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
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#define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
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#define HNS3_PPP_PF_ERR_INT_EN 0x0003
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#define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003
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#define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F
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#define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
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#define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F
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#define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
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#define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF
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#define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
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#define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB
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#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
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#define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
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#define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
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#define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
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#define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
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#define HNS3_PPU_PF_INT_MSIX_MASK 0x27
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#define HNS3_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28)
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#define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101
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#define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
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#define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0)
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#define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
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#define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
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#define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
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#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
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#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
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#define HNS3_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
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#define HNS3_SSU_PORT_INT_MSIX_MASK 0x7BFF
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#define HNS3_RESET_PROCESS_MS 200
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struct hns3_hw_blk {
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const char *name;
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int (*enable_err_intr)(struct hns3_adapter *hns, bool en);
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};
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struct hns3_hw_error {
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uint32_t int_msk;
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const char *msg;
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enum hns3_reset_level reset_level;
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};
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int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);
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void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
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void hns3_intr_unregister(const struct rte_intr_handle *hdl,
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rte_intr_callback_fn cb_fn, void *cb_arg);
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void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable);
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int hns3_reset_init(struct hns3_hw *hw);
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void hns3_wait_callback(void *param);
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void hns3_schedule_reset(struct hns3_adapter *hns);
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void hns3_schedule_delayed_reset(struct hns3_adapter *hns);
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int hns3_reset_req_hw_reset(struct hns3_adapter *hns);
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int hns3_reset_process(struct hns3_adapter *hns,
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enum hns3_reset_level reset_level);
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void hns3_reset_abort(struct hns3_adapter *hns);
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#endif /* _HNS3_INTR_H_ */
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