mirror of https://github.com/F-Stack/f-stack.git
276 lines
8.4 KiB
C
276 lines
8.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2018-2020 NXP
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*/
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#ifndef _ENETC_HW_H_
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#define _ENETC_HW_H_
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#include <rte_io.h>
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#define BIT(x) ((uint64_t)1 << ((x)))
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/* ENETC device IDs */
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#define ENETC_DEV_ID_VF 0xef00
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#define ENETC_DEV_ID 0xe100
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/* BD RING ALIGNMENT */
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#define ENETC_BD_RING_ALIGN 128
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/* ENETC register block BAR */
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#define ENETC_BAR_REGS 0x0
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/* SI regs, offset: 0h */
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#define ENETC_SIMR 0x0
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#define ENETC_SIMR_EN BIT(31)
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#define ENETC_SIPMAR0 0x80
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#define ENETC_SIPMAR1 0x84
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#define ENETC_SICAPR0 0x900
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#define ENETC_SICAPR1 0x904
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#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
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#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
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#define ENETC_SICCAPR 0x1200
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/* enum for BD type */
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enum enetc_bdr_type {TX, RX};
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#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 \
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+ (off))
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/* RX BDR reg offsets */
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#define ENETC_RBMR 0x0 /* RX BDR mode register*/
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#define ENETC_RBMR_EN BIT(31)
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#define ENETC_RBSR 0x4 /* Rx BDR status register*/
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#define ENETC_RBBSR 0x8 /* Rx BDR buffer size register*/
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#define ENETC_RBCIR 0xc /* Rx BDR consumer index register*/
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#define ENETC_RBBAR0 0x10 /* Rx BDR base address register 0 */
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#define ENETC_RBBAR1 0x14 /* Rx BDR base address register 1*/
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#define ENETC_RBPIR 0x18 /* Rx BDR producer index register*/
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#define ENETC_RBLENR 0x20 /* Rx BDR length register*/
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#define ENETC_RBIER 0xa0 /* Rx BDR interrupt enable register*/
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#define ENETC_RBIER_RXTIE BIT(0)
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#define ENETC_RBIDR 0xa4 /* Rx BDR interrupt detect register*/
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#define ENETC_RBICIR0 0xa8 /* Rx BDR inetrrupt coalescing register 0*/
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#define ENETC_RBICIR0_ICEN BIT(31)
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#define ENETC_TBMR 0x0 /* Tx BDR mode register (TBMR) 32 RW */
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#define ENETC_TBSR 0x4 /* x BDR status register (TBSR) 32 RO */
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#define ENETC_TBBAR0 0x10 /* Tx BDR base address register 0 (TBBAR0) 32 RW */
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#define ENETC_TBBAR1 0x14 /* Tx BDR base address register 1 (TBBAR1) 32 RW */
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#define ENETC_TBCIR 0x18 /* Tx BDR consumer index register (TBCIR) 32 RW */
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#define ENETC_TBCISR 0x1C /* Tx BDR consumer index shadow register 32 RW */
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#define ENETC_TBIER 0xA0 /* Tx BDR interrupt enable register 32 RW */
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#define ENETC_TBIDR 0xA4 /* Tx BDR interrupt detect register 32 RO */
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#define ENETC_TBICR0 0xA8 /* Tx BDR interrupt coalescing register 0 32 RW */
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#define ENETC_TBICR1 0xAC /* Tx BDR interrupt coalescing register 1 32 RW */
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#define ENETC_TBLENR 0x20
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#define ENETC_TBCISR_IDX_MASK 0xffff
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#define ENETC_TBIER_TXFIE BIT(1)
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#define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
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#define ENETC_TBMR_EN BIT(31)
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/* Port regs, offset: 1_0000h */
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#define ENETC_PORT_BASE 0x10000
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#define ENETC_PMR 0x00000
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#define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18))
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#define ENETC_PSR 0x00004 /* RO */
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#define ENETC_PSIPMR 0x00018
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#define ENETC_PSIPMR_SET_UP(n) (0x1 << (n)) /* n = SI index */
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#define ENETC_PSIPMR_SET_MP(n) (0x1 << ((n) + 16))
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#define ENETC_PSIPMAR0(n) (0x00100 + (n) * 0x20)
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#define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20)
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#define ENETC_PCAPR0 0x00900
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#define ENETC_PCAPR1 0x00904
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#define ENETC_PM0_RX_FIFO 0x801C
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#define ENETC_PM0_IF_MODE 0x8300
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#define ENETC_PM1_IF_MODE 0x9300
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#define ENETC_PMO_IFM_RG BIT(2)
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#define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
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#define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
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#define ENETC_PM0_IFM_XGMII BIT(12)
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#define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10)
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#define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff)
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#define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
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#define ENETC_PM0_CMD_CFG 0x08008
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#define ENETC_PM0_TX_EN BIT(0)
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#define ENETC_PM0_RX_EN BIT(1)
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#define ENETC_PM0_CRC BIT(6)
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#define ENETC_PAR_PORT_CFG 0x03050
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#define L3_CKSUM BIT(0)
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#define L4_CKSUM BIT(1)
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#define ENETC_PM0_MAXFRM 0x08014
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#define ENETC_SET_TX_MTU(val) ((val) << 16)
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#define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
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#define ENETC_PTXMBAR 0x0608
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/* n = TC index [0..7] */
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#define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4)
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#define ENETC_PM0_STATUS 0x08304
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#define ENETC_LINK_MODE 0x0000000000080000ULL
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#define ENETC_LINK_STATUS 0x0000000000010000ULL
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#define ENETC_LINK_SPEED_MASK 0x0000000000060000ULL
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#define ENETC_LINK_SPEED_10M 0x0ULL
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#define ENETC_LINK_SPEED_100M 0x0000000000020000ULL
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#define ENETC_LINK_SPEED_1G 0x0000000000040000ULL
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/* Global regs, offset: 2_0000h */
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#define ENETC_GLOBAL_BASE 0x20000
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#define ENETC_G_EIPBRR0 0x00bf8
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#define ENETC_G_EIPBRR1 0x00bfc
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/* MAC Counters */
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/* Config register to reset counters*/
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#define ENETC_PM0_STAT_CONFIG 0x080E0
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/* Receive frames counter without error */
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#define ENETC_PM0_RFRM 0x08120
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/* Receive packets counter, good + bad */
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#define ENETC_PM0_RPKT 0x08160
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/* Received octets, good + bad */
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#define ENETC_PM0_REOCT 0x08120
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/* Transmit octets, good + bad */
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#define ENETC_PM0_TEOCT 0x08200
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/* Transmit frames counter without error */
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#define ENETC_PM0_TFRM 0x08220
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/* Transmit packets counter, good + bad */
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#define ENETC_PM0_TPKT 0x08260
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/* Dropped not Truncated packets counter */
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#define ENETC_PM0_RDRNTP 0x081C8
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/* Dropped + trucated packets counter */
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#define ENETC_PM0_RDRP 0x08158
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/* Receive packets error counter */
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#define ENETC_PM0_RERR 0x08138
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/* Transmit packets error counter */
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#define ENETC_PM0_TERR 0x08238
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/* Stats Reset Bit*/
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#define ENETC_CLEAR_STATS BIT(2)
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#define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
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#define ENETC_G_EPFBLPR1_XGMII 0x80000000
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/* general register accessors */
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#define enetc_rd_reg(reg) rte_read32((void *)(reg))
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#define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg))
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#define enetc_rd(hw, off) enetc_rd_reg((size_t)(hw)->reg + (off))
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#define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val)
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/* port register accessors - PF only */
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#define enetc_port_rd(hw, off) enetc_rd_reg((size_t)(hw)->port + (off))
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#define enetc_port_wr(hw, off, val) \
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enetc_wr_reg((size_t)(hw)->port + (off), val)
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/* global register accessors - PF only */
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#define enetc_global_rd(hw, off) \
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enetc_rd_reg((size_t)(hw)->global + (off))
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#define enetc_global_wr(hw, off, val) \
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enetc_wr_reg((size_t)(hw)->global + (off), val)
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/* BDR register accessors, see ENETC_BDR() */
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#define enetc_bdr_rd(hw, t, n, off) \
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enetc_rd(hw, ENETC_BDR(t, n, off))
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#define enetc_bdr_wr(hw, t, n, off, val) \
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enetc_wr(hw, ENETC_BDR(t, n, off), val)
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#define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
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#define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
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#define enetc_txbdr_wr(hw, n, off, val) \
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enetc_bdr_wr(hw, TX, n, off, val)
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#define enetc_rxbdr_wr(hw, n, off, val) \
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enetc_bdr_wr(hw, RX, n, off, val)
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#define ENETC_TX_ADDR(txq, addr) ((void *)((txq)->enetc_txbdr + (addr)))
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#define ENETC_TXBD_FLAGS_IE BIT(13)
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#define ENETC_TXBD_FLAGS_F BIT(15)
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/* ENETC Parsed values (Little Endian) */
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#define ENETC_PARSE_ERROR 0x8000
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#define ENETC_PKT_TYPE_ETHER 0x0060
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#define ENETC_PKT_TYPE_IPV4 0x0000
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#define ENETC_PKT_TYPE_IPV6 0x0020
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#define ENETC_PKT_TYPE_IPV4_TCP \
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(0x0010 | ENETC_PKT_TYPE_IPV4)
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#define ENETC_PKT_TYPE_IPV6_TCP \
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(0x0010 | ENETC_PKT_TYPE_IPV6)
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#define ENETC_PKT_TYPE_IPV4_UDP \
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(0x0011 | ENETC_PKT_TYPE_IPV4)
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#define ENETC_PKT_TYPE_IPV6_UDP \
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(0x0011 | ENETC_PKT_TYPE_IPV6)
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#define ENETC_PKT_TYPE_IPV4_SCTP \
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(0x0013 | ENETC_PKT_TYPE_IPV4)
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#define ENETC_PKT_TYPE_IPV6_SCTP \
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(0x0013 | ENETC_PKT_TYPE_IPV6)
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#define ENETC_PKT_TYPE_IPV4_ICMP \
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(0x0003 | ENETC_PKT_TYPE_IPV4)
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#define ENETC_PKT_TYPE_IPV6_ICMP \
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(0x0003 | ENETC_PKT_TYPE_IPV6)
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/* PCI device info */
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struct enetc_hw {
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void *reg; /* SI registers, used by all PCI functions */
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void *port; /* Port registers, PF only */
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void *global; /* IP global registers, PF only */
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};
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struct enetc_eth_mac_info {
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uint8_t addr[RTE_ETHER_ADDR_LEN];
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uint8_t perm_addr[RTE_ETHER_ADDR_LEN];
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uint8_t get_link_status;
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};
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struct enetc_eth_hw {
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struct rte_eth_dev *ndev;
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struct enetc_hw hw;
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uint16_t device_id;
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uint16_t vendor_id;
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uint8_t revision_id;
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struct enetc_eth_mac_info mac;
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};
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/* Transmit Descriptor */
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struct enetc_tx_desc {
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uint64_t addr;
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uint16_t frm_len;
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uint16_t buf_len;
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uint32_t flags_errors;
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};
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/* TX Buffer Descriptors (BD) */
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struct enetc_tx_bd {
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uint64_t addr;
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uint16_t buf_len;
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uint16_t frm_len;
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uint16_t err_csum;
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uint16_t flags;
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};
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/* RX buffer descriptor */
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union enetc_rx_bd {
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struct {
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uint64_t addr;
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uint8_t reserved[8];
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} w;
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struct {
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uint16_t inet_csum;
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uint16_t parse_summary;
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uint32_t rss_hash;
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uint16_t buf_len;
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uint16_t vlan_opt;
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union {
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struct {
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uint16_t flags;
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uint16_t error;
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};
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uint32_t lstatus;
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};
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} r;
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};
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#endif
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