mirror of https://github.com/F-Stack/f-stack.git
602 lines
14 KiB
C
602 lines
14 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Cavium, Inc
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*/
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#include <assert.h>
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#include <string.h>
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#include <unistd.h>
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#include <rte_branch_prediction.h>
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#include <rte_common.h>
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#include <rte_errno.h>
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#include <rte_memzone.h>
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#include <rte_string_fns.h>
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#include "otx_cryptodev_hw_access.h"
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#include "otx_cryptodev_mbox.h"
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#include "cpt_pmd_logs.h"
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#include "cpt_hw_types.h"
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/*
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* VF HAL functions
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* Access its own BAR0/4 registers by passing VF number as 0.
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* OS/PCI maps them accordingly.
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*/
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static int
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otx_cpt_vf_init(struct cpt_vf *cptvf)
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{
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int ret = 0;
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/* Check ready with PF */
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/* Gets chip ID / device Id from PF if ready */
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ret = otx_cpt_check_pf_ready(cptvf);
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if (ret) {
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CPT_LOG_ERR("%s: PF not responding to READY msg",
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cptvf->dev_name);
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ret = -EBUSY;
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goto exit;
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}
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CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
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exit:
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return ret;
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}
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/*
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* Read Interrupt status of the VF
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*
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* @param cptvf cptvf structure
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*/
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static uint64_t
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otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)
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{
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return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));
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}
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/*
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* Clear mailbox interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.mbox = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/*
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* Clear instruction NCB read error interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.irde = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/*
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* Clear NCB result write response error interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.nwrp = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/*
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* Clear swerr interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.swerr = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/*
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* Clear hwerr interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.hwerr = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/*
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* Clear translation fault interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.fault = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/*
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* Clear doorbell overflow interrupt of the VF
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*
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* @param cptvf cptvf structure
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*/
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static void
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otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
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{
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cptx_vqx_misc_int_t vqx_misc_int;
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vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0));
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/* W1C for the VF */
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vqx_misc_int.s.dovf = 1;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
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}
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/* Write to VQX_CTL register
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*/
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static void
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otx_cpt_write_vq_ctl(struct cpt_vf *cptvf, bool val)
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{
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cptx_vqx_ctl_t vqx_ctl;
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vqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_CTL(0, 0));
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vqx_ctl.s.ena = val;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_CTL(0, 0), vqx_ctl.u);
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}
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/* Write to VQX_INPROG register
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*/
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static void
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otx_cpt_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)
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{
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cptx_vqx_inprog_t vqx_inprg;
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vqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_INPROG(0, 0));
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vqx_inprg.s.inflight = val;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_INPROG(0, 0), vqx_inprg.u);
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}
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/* Write to VQX_DONE_WAIT NUMWAIT register
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*/
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static void
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otx_cpt_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)
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{
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cptx_vqx_done_wait_t vqx_dwait;
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vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_DONE_WAIT(0, 0));
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vqx_dwait.s.num_wait = val;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
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}
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/* Write to VQX_DONE_WAIT NUM_WAIT register
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*/
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static void
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otx_cpt_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)
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{
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cptx_vqx_done_wait_t vqx_dwait;
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vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_DONE_WAIT(0, 0));
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vqx_dwait.s.time_wait = val;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
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}
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/* Write to VQX_SADDR register
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*/
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static void
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otx_cpt_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)
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{
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cptx_vqx_saddr_t vqx_saddr;
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vqx_saddr.u = val;
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CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
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CPTX_VQX_SADDR(0, 0), vqx_saddr.u);
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}
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static void
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otx_cpt_vfvq_init(struct cpt_vf *cptvf)
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{
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uint64_t base_addr = 0;
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/* Disable the VQ */
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otx_cpt_write_vq_ctl(cptvf, 0);
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/* Reset the doorbell */
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otx_cpt_write_vq_doorbell(cptvf, 0);
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/* Clear inflight */
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otx_cpt_write_vq_inprog(cptvf, 0);
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/* Write VQ SADDR */
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base_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);
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otx_cpt_write_vq_saddr(cptvf, base_addr);
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/* Configure timerhold / coalescence */
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otx_cpt_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);
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otx_cpt_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);
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/* Enable the VQ */
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otx_cpt_write_vq_ctl(cptvf, 1);
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}
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static int
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cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)
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{
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int err;
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/* Convey VQ LEN to PF */
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err = otx_cpt_send_vq_size_msg(cptvf);
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if (err) {
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CPT_LOG_ERR("%s: PF not responding to QLEN msg",
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cptvf->dev_name);
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err = -EBUSY;
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goto cleanup;
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}
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/* CPT VF device initialization */
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otx_cpt_vfvq_init(cptvf);
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/* Send msg to PF to assign currnet Q to required group */
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cptvf->vfgrp = group;
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err = otx_cpt_send_vf_grp_msg(cptvf, group);
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if (err) {
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CPT_LOG_ERR("%s: PF not responding to VF_GRP msg",
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cptvf->dev_name);
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err = -EBUSY;
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goto cleanup;
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}
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CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
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return 0;
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cleanup:
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return err;
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}
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void
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otx_cpt_poll_misc(struct cpt_vf *cptvf)
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{
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uint64_t intr;
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intr = otx_cpt_read_vf_misc_intr_status(cptvf);
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if (!intr)
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return;
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/* Check for MISC interrupt types */
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if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
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CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
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cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
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otx_cpt_handle_mbox_intr(cptvf);
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otx_cpt_clear_mbox_intr(cptvf);
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} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
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otx_cpt_clear_irde_intr(cptvf);
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CPT_LOG_DP_DEBUG("%s: Instruction NCB read error interrupt "
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"0x%lx on CPT VF %d", cptvf->dev_name,
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(unsigned int long)intr, cptvf->vfid);
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} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {
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otx_cpt_clear_nwrp_intr(cptvf);
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CPT_LOG_DP_DEBUG("%s: NCB response write error interrupt 0x%lx"
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" on CPT VF %d", cptvf->dev_name,
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(unsigned int long)intr, cptvf->vfid);
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} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {
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otx_cpt_clear_swerr_intr(cptvf);
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CPT_LOG_DP_DEBUG("%s: Software error interrupt 0x%lx on CPT VF "
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"%d", cptvf->dev_name, (unsigned int long)intr,
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cptvf->vfid);
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} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {
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otx_cpt_clear_hwerr_intr(cptvf);
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CPT_LOG_DP_DEBUG("%s: Hardware error interrupt 0x%lx on CPT VF "
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"%d", cptvf->dev_name, (unsigned int long)intr,
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cptvf->vfid);
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} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {
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otx_cpt_clear_fault_intr(cptvf);
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CPT_LOG_DP_DEBUG("%s: Translation fault interrupt 0x%lx on CPT VF "
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"%d", cptvf->dev_name, (unsigned int long)intr,
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cptvf->vfid);
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} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {
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otx_cpt_clear_dovf_intr(cptvf);
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CPT_LOG_DP_DEBUG("%s: Doorbell overflow interrupt 0x%lx on CPT VF "
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"%d", cptvf->dev_name, (unsigned int long)intr,
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cptvf->vfid);
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} else
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CPT_LOG_DP_ERR("%s: Unhandled interrupt 0x%lx in CPT VF %d",
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cptvf->dev_name, (unsigned int long)intr,
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cptvf->vfid);
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}
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int
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otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
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{
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memset(cptvf, 0, sizeof(struct cpt_vf));
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/* Bar0 base address */
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cptvf->reg_base = reg_base;
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/* Save device name */
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strlcpy(cptvf->dev_name, name, (sizeof(cptvf->dev_name)));
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cptvf->pdev = pdev;
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/* To clear if there are any pending mbox msgs */
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otx_cpt_poll_misc(cptvf);
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if (otx_cpt_vf_init(cptvf)) {
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CPT_LOG_ERR("Failed to initialize CPT VF device");
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return -1;
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}
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return 0;
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}
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int
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otx_cpt_deinit_device(void *dev)
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{
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struct cpt_vf *cptvf = (struct cpt_vf *)dev;
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/* Do misc work one last time */
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otx_cpt_poll_misc(cptvf);
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return 0;
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}
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int
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otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance)
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{
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int ret = -ENOENT, len, qlen, i;
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int chunk_len, chunks, chunk_size;
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struct cpt_vf *cptvf = (struct cpt_vf *)dev;
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struct cpt_instance *cpt_instance;
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struct command_chunk *chunk_head = NULL, *chunk_prev = NULL;
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struct command_chunk *chunk = NULL;
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uint8_t *mem;
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const struct rte_memzone *rz;
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uint64_t dma_addr = 0, alloc_len, used_len;
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uint64_t *next_ptr;
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uint64_t pg_sz = sysconf(_SC_PAGESIZE);
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CPT_LOG_DP_DEBUG("Initializing cpt resource %s", cptvf->dev_name);
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cpt_instance = &cptvf->instance;
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memset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));
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memset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));
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/* Chunks are of fixed size buffers */
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chunks = DEFAULT_CMD_QCHUNKS;
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chunk_len = DEFAULT_CMD_QCHUNK_SIZE;
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qlen = chunks * chunk_len;
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/* Chunk size includes 8 bytes of next chunk ptr */
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chunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;
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/* For command chunk structures */
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len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);
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/* For pending queue */
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len += qlen * RTE_ALIGN(sizeof(struct rid), 8);
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/* So that instruction queues start as pg size aligned */
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len = RTE_ALIGN(len, pg_sz);
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/* For Instruction queues */
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len += chunks * RTE_ALIGN(chunk_size, 128);
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/* Wastage after instruction queues */
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len = RTE_ALIGN(len, pg_sz);
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rz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,
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RTE_MEMZONE_SIZE_HINT_ONLY |
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RTE_MEMZONE_256MB,
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RTE_CACHE_LINE_SIZE);
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if (!rz) {
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ret = rte_errno;
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goto cleanup;
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}
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mem = rz->addr;
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dma_addr = rz->phys_addr;
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alloc_len = len;
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memset(mem, 0, len);
|
|
|
|
cpt_instance->rsvd = (uintptr_t)rz;
|
|
|
|
/* Pending queue setup */
|
|
cptvf->pqueue.rid_queue = (struct rid *)mem;
|
|
cptvf->pqueue.enq_tail = 0;
|
|
cptvf->pqueue.deq_head = 0;
|
|
cptvf->pqueue.pending_count = 0;
|
|
|
|
mem += qlen * RTE_ALIGN(sizeof(struct rid), 8);
|
|
len -= qlen * RTE_ALIGN(sizeof(struct rid), 8);
|
|
dma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);
|
|
|
|
/* Alignment wastage */
|
|
used_len = alloc_len - len;
|
|
mem += RTE_ALIGN(used_len, pg_sz) - used_len;
|
|
len -= RTE_ALIGN(used_len, pg_sz) - used_len;
|
|
dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;
|
|
|
|
/* Init instruction queues */
|
|
chunk_head = &cptvf->cqueue.chead[0];
|
|
i = qlen;
|
|
|
|
chunk_prev = NULL;
|
|
for (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {
|
|
int csize;
|
|
|
|
chunk = &cptvf->cqueue.chead[i];
|
|
chunk->head = mem;
|
|
chunk->dma_addr = dma_addr;
|
|
|
|
csize = RTE_ALIGN(chunk_size, 128);
|
|
mem += csize;
|
|
dma_addr += csize;
|
|
len -= csize;
|
|
|
|
if (chunk_prev) {
|
|
next_ptr = (uint64_t *)(chunk_prev->head +
|
|
chunk_size - 8);
|
|
*next_ptr = (uint64_t)chunk->dma_addr;
|
|
}
|
|
chunk_prev = chunk;
|
|
}
|
|
/* Circular loop */
|
|
next_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);
|
|
*next_ptr = (uint64_t)chunk_head->dma_addr;
|
|
|
|
assert(!len);
|
|
|
|
/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */
|
|
cptvf->qsize = chunk_size / 8;
|
|
cptvf->cqueue.qhead = chunk_head->head;
|
|
cptvf->cqueue.idx = 0;
|
|
cptvf->cqueue.cchunk = 0;
|
|
|
|
if (cpt_vq_init(cptvf, group)) {
|
|
CPT_LOG_ERR("Failed to initialize CPT VQ of device %s",
|
|
cptvf->dev_name);
|
|
ret = -EBUSY;
|
|
goto cleanup;
|
|
}
|
|
|
|
*instance = cpt_instance;
|
|
|
|
CPT_LOG_DP_DEBUG("Crypto device (%s) initialized", cptvf->dev_name);
|
|
|
|
return 0;
|
|
cleanup:
|
|
rte_memzone_free(rz);
|
|
*instance = NULL;
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
otx_cpt_put_resource(struct cpt_instance *instance)
|
|
{
|
|
struct cpt_vf *cptvf = (struct cpt_vf *)instance;
|
|
struct rte_memzone *rz;
|
|
|
|
if (!cptvf) {
|
|
CPT_LOG_ERR("Invalid CPTVF handle");
|
|
return -EINVAL;
|
|
}
|
|
|
|
CPT_LOG_DP_DEBUG("Releasing cpt device %s", cptvf->dev_name);
|
|
|
|
rz = (struct rte_memzone *)instance->rsvd;
|
|
rte_memzone_free(rz);
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
otx_cpt_start_device(void *dev)
|
|
{
|
|
int rc;
|
|
struct cpt_vf *cptvf = (struct cpt_vf *)dev;
|
|
|
|
rc = otx_cpt_send_vf_up(cptvf);
|
|
if (rc) {
|
|
CPT_LOG_ERR("Failed to mark CPT VF device %s UP, rc = %d",
|
|
cptvf->dev_name, rc);
|
|
return -EFAULT;
|
|
}
|
|
|
|
if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) {
|
|
CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
|
|
"device %s", cptvf->vftype, cptvf->dev_name);
|
|
return -ENOENT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
otx_cpt_stop_device(void *dev)
|
|
{
|
|
int rc;
|
|
uint32_t pending, retries = 5;
|
|
struct cpt_vf *cptvf = (struct cpt_vf *)dev;
|
|
|
|
/* Wait for pending entries to complete */
|
|
pending = otx_cpt_read_vq_doorbell(cptvf);
|
|
while (pending) {
|
|
CPT_LOG_DP_DEBUG("%s: Waiting for pending %u cmds to complete",
|
|
cptvf->dev_name, pending);
|
|
sleep(1);
|
|
pending = otx_cpt_read_vq_doorbell(cptvf);
|
|
retries--;
|
|
if (!retries)
|
|
break;
|
|
}
|
|
|
|
if (!retries && pending) {
|
|
CPT_LOG_ERR("%s: Timeout waiting for commands(%u)",
|
|
cptvf->dev_name, pending);
|
|
return;
|
|
}
|
|
|
|
rc = otx_cpt_send_vf_down(cptvf);
|
|
if (rc) {
|
|
CPT_LOG_ERR("Failed to bring down vf %s, rc %d",
|
|
cptvf->dev_name, rc);
|
|
return;
|
|
}
|
|
}
|