mirror of https://github.com/F-Stack/f-stack.git
113 lines
2.4 KiB
C
113 lines
2.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015 Cavium, Inc
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* Copyright(c) 2020 Arm Limited
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*/
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#ifndef _RTE_CYCLES_ARM64_H_
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#define _RTE_CYCLES_ARM64_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "generic/rte_cycles.h"
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/** Read generic counter frequency */
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static __rte_always_inline uint64_t
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__rte_arm64_cntfrq(void)
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{
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uint64_t freq;
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asm volatile("mrs %0, cntfrq_el0" : "=r" (freq));
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return freq;
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}
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/** Read generic counter */
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static __rte_always_inline uint64_t
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__rte_arm64_cntvct(void)
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{
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uint64_t tsc;
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asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
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return tsc;
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}
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static __rte_always_inline uint64_t
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__rte_arm64_cntvct_precise(void)
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{
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asm volatile("isb" : : : "memory");
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return __rte_arm64_cntvct();
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}
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/**
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* Read the time base register.
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*
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* @return
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* The time base for this lcore.
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*/
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#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
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/**
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* This call is portable to any ARMv8 architecture, however, typically
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* cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
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*/
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static __rte_always_inline uint64_t
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rte_rdtsc(void)
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{
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return __rte_arm64_cntvct();
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}
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#else
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/**
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* This is an alternative method to enable rte_rdtsc() with high resolution
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* PMU cycles counter.The cycle counter runs at cpu frequency and this scheme
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* uses ARMv8 PMU subsystem to get the cycle counter at userspace, However,
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* access to PMU cycle counter from user space is not enabled by default in
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* arm64 linux kernel.
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* It is possible to enable cycle counter at user space access by configuring
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* the PMU from the privileged mode (kernel space).
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*
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* asm volatile("msr pmintenset_el1, %0" : : "r" ((u64)(0 << 31)));
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* asm volatile("msr pmcntenset_el0, %0" :: "r" BIT(31));
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* asm volatile("msr pmuserenr_el0, %0" : : "r"(BIT(0) | BIT(2)));
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* asm volatile("mrs %0, pmcr_el0" : "=r" (val));
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* val |= (BIT(0) | BIT(2));
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* isb();
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* asm volatile("msr pmcr_el0, %0" : : "r" (val));
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*
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*/
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/** Read PMU cycle counter */
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static __rte_always_inline uint64_t
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__rte_arm64_pmccntr(void)
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{
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uint64_t tsc;
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asm volatile("mrs %0, pmccntr_el0" : "=r"(tsc));
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return tsc;
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}
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static __rte_always_inline uint64_t
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rte_rdtsc(void)
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{
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return __rte_arm64_pmccntr();
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}
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#endif
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static __rte_always_inline uint64_t
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rte_rdtsc_precise(void)
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{
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asm volatile("isb" : : : "memory");
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return rte_rdtsc();
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}
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static __rte_always_inline uint64_t
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rte_get_tsc_cycles(void)
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{
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return rte_rdtsc();
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_CYCLES_ARM64_H_ */
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