mirror of https://github.com/F-Stack/f-stack.git
500 lines
13 KiB
C
500 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_EP_RAWDEV_H_
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#define _OTX2_EP_RAWDEV_H_
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#include <rte_byteorder.h>
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#include <rte_spinlock.h>
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/* IQ instruction req types */
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#define SDP_REQTYPE_NONE (0)
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#define SDP_REQTYPE_NORESP (1)
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#define SDP_REQTYPE_NORESP_GATHER (2)
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/* Input Request Header format */
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struct sdp_instr_irh {
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/* Request ID */
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uint64_t rid:16;
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/* PCIe port to use for response */
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uint64_t pcie_port:3;
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/* Scatter indicator 1=scatter */
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uint64_t scatter:1;
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/* Size of Expected result OR no. of entries in scatter list */
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uint64_t rlenssz:14;
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/* Desired destination port for result */
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uint64_t dport:6;
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/* Opcode Specific parameters */
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uint64_t param:8;
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/* Opcode for the return packet */
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uint64_t opcode:16;
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};
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/* SDP 32B instruction format */
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struct sdp_instr_32B {
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/* Pointer where the input data is available. */
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uint64_t dptr;
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/* SDP Instruction Header. */
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uint64_t ih;
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/** Pointer where the response for a RAW mode packet
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* will be written by OCTEON TX2.
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*/
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uint64_t rptr;
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/* Input Request Header. Additional info about the input. */
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uint64_t irh;
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};
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#define SDP_32B_INSTR_SIZE (sizeof(sdp_instr_32B))
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/* SDP 64B instruction format */
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struct sdp_instr_64B {
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/* Pointer where the input data is available. */
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uint64_t dptr;
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/* SDP Instruction Header. */
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uint64_t ih;
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/** Pointer where the response for a RAW mode packet
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* will be written by OCTEON TX2.
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*/
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uint64_t rptr;
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/* Input Request Header. */
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uint64_t irh;
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/* Additional headers available in a 64-byte instruction. */
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uint64_t exhdr[4];
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};
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#define SDP_64B_INSTR_SIZE (sizeof(sdp_instr_64B))
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struct sdp_soft_instr {
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/** Input data pointer. It is either pointing directly to input data
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* or to a gather list.
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*/
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void *dptr;
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/** Response from OCTEON TX2 comes at this address. It is either
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* directlty pointing to output data buffer or to a scatter list.
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*/
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void *rptr;
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/* The instruction header. All input commands have this field. */
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struct sdp_instr_ih ih;
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/* Input request header. */
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struct sdp_instr_irh irh;
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/** The PCI instruction to be sent to OCTEON TX2. This is stored in the
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* instr to retrieve the physical address of buffers when instr is
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* freed.
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*/
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struct sdp_instr_64B command;
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/** If a gather list was allocated, this ptr points to the buffer used
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* for the gather list. The gather list has to be 8B aligned, so this
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* value may be different from dptr.
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*/
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void *gather_ptr;
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/* Total data bytes transferred in the gather mode request. */
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uint64_t gather_bytes;
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/** If a scatter list was allocated, this ptr points to the buffer used
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* for the scatter list. The scatter list has to be 8B aligned, so
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* this value may be different from rptr.
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*/
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void *scatter_ptr;
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/* Total data bytes to be received in the scatter mode request. */
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uint64_t scatter_bytes;
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/* IQ number to which this instruction has to be submitted. */
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uint32_t q_no;
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/* IQ instruction request type. */
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uint32_t reqtype;
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};
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#define SDP_SOFT_INSTR_SIZE (sizeof(sdp_soft_instr))
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/* SDP IQ request list */
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struct sdp_instr_list {
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void *buf;
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uint32_t reqtype;
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};
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#define SDP_IQREQ_LIST_SIZE (sizeof(struct sdp_instr_list))
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/* Input Queue statistics. Each input queue has four stats fields. */
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struct sdp_iq_stats {
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uint64_t instr_posted; /* Instructions posted to this queue. */
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uint64_t instr_processed; /* Instructions processed in this queue. */
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uint64_t instr_dropped; /* Instructions that could not be processed */
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};
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/* Structure to define the configuration attributes for each Input queue. */
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struct sdp_iq_config {
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/* Max number of IQs available */
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uint16_t max_iqs;
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/* Command size - 32 or 64 bytes */
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uint16_t instr_type;
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/* Pending list size, usually set to the sum of the size of all IQs */
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uint32_t pending_list_size;
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};
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/** The instruction (input) queue.
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* The input queue is used to post raw (instruction) mode data or packet data
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* to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
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* such structure to represent it.
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*/
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struct sdp_instr_queue {
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/* A spinlock to protect access to the input ring. */
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rte_spinlock_t lock;
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rte_spinlock_t post_lock;
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struct sdp_device *sdp_dev;
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rte_atomic64_t iq_flush_running;
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uint32_t q_no;
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uint32_t pkt_in_done;
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/* Flag for 64 byte commands. */
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uint32_t iqcmd_64B:1;
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uint32_t rsvd:17;
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uint32_t status:8;
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/* Number of descriptors in this ring. */
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uint32_t nb_desc;
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/* Input ring index, where the driver should write the next packet */
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uint32_t host_write_index;
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/* Input ring index, where the OCTEON TX2 should read the next packet */
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uint32_t otx_read_index;
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/** This index aids in finding the window in the queue where OCTEON TX2
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* has read the commands.
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*/
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uint32_t flush_index;
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/* This keeps track of the instructions pending in this queue. */
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rte_atomic64_t instr_pending;
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uint32_t reset_instr_cnt;
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/* Pointer to the Virtual Base addr of the input ring. */
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uint8_t *base_addr;
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/* This IQ request list */
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struct sdp_instr_list *req_list;
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/* SDP doorbell register for the ring. */
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void *doorbell_reg;
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/* SDP instruction count register for this ring. */
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void *inst_cnt_reg;
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/* Number of instructions pending to be posted to OCTEON TX2. */
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uint32_t fill_cnt;
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/* Statistics for this input queue. */
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struct sdp_iq_stats stats;
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/* DMA mapped base address of the input descriptor ring. */
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uint64_t base_addr_dma;
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/* Memory zone */
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const struct rte_memzone *iq_mz;
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};
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/* DROQ packet format for application i/f. */
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struct sdp_droq_pkt {
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/* DROQ packet data buffer pointer. */
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uint8_t *data;
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/* DROQ packet data length */
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uint32_t len;
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uint32_t misc;
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};
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/** Descriptor format.
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* The descriptor ring is made of descriptors which have 2 64-bit values:
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* -# Physical (bus) address of the data buffer.
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* -# Physical (bus) address of a sdp_droq_info structure.
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* The device DMA's incoming packets and its information at the address
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* given by these descriptor fields.
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*/
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struct sdp_droq_desc {
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/* The buffer pointer */
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uint64_t buffer_ptr;
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/* The Info pointer */
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uint64_t info_ptr;
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};
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#define SDP_DROQ_DESC_SIZE (sizeof(struct sdp_droq_desc))
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/* Receive Header */
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union sdp_rh {
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uint64_t rh64;
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};
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#define SDP_RH_SIZE (sizeof(union sdp_rh))
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/** Information about packet DMA'ed by OCTEON TX2.
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* The format of the information available at Info Pointer after OCTEON TX2
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* has posted a packet. Not all descriptors have valid information. Only
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* the Info field of the first descriptor for a packet has information
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* about the packet.
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*/
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struct sdp_droq_info {
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/* The Output Receive Header. */
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union sdp_rh rh;
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/* The Length of the packet. */
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uint64_t length;
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};
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#define SDP_DROQ_INFO_SIZE (sizeof(struct sdp_droq_info))
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/** Pointer to data buffer.
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* Driver keeps a pointer to the data buffer that it made available to
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* the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
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* addresses, this field is required for the driver to keep track of
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* the virtual address pointers.
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*/
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struct sdp_recv_buffer {
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/* Packet buffer, including meta data. */
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void *buffer;
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/* Data in the packet buffer. */
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/* uint8_t *data; */
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};
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#define SDP_DROQ_RECVBUF_SIZE (sizeof(struct sdp_recv_buffer))
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/* DROQ statistics. Each output queue has four stats fields. */
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struct sdp_droq_stats {
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/* Number of packets received in this queue. */
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uint64_t pkts_received;
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/* Bytes received by this queue. */
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uint64_t bytes_received;
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/* Num of failures of rte_pktmbuf_alloc() */
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uint64_t rx_alloc_failure;
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};
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/* Structure to define the configuration attributes for each Output queue. */
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struct sdp_oq_config {
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/* Max number of OQs available */
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uint16_t max_oqs;
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/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
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uint16_t info_ptr;
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/** The number of buffers that were consumed during packet processing by
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* the driver on this Output queue before the driver attempts to
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* replenish the descriptor ring with new buffers.
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*/
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uint32_t refill_threshold;
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};
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/* The Descriptor Ring Output Queue(DROQ) structure. */
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struct sdp_droq {
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/* A spinlock to protect access to this ring. */
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rte_spinlock_t lock;
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struct sdp_device *sdp_dev;
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/* The 8B aligned descriptor ring starts at this address. */
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struct sdp_droq_desc *desc_ring;
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uint32_t q_no;
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uint32_t last_pkt_count;
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/* Driver should read the next packet at this index */
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uint32_t read_idx;
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/* OCTEON TX2 will write the next packet at this index */
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uint32_t write_idx;
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/* At this index, the driver will refill the descriptor's buffer */
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uint32_t refill_idx;
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/* Packets pending to be processed */
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rte_atomic64_t pkts_pending;
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/* Number of descriptors in this ring. */
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uint32_t nb_desc;
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/* The number of descriptors pending to refill. */
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uint32_t refill_count;
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uint32_t refill_threshold;
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/* The 8B aligned info ptrs begin from this address. */
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struct sdp_droq_info *info_list;
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/* receive buffer list contains virtual addresses of the buffers. */
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struct sdp_recv_buffer *recv_buf_list;
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/* The size of each buffer pointed by the buffer pointer. */
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uint32_t buffer_size;
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/** Pointer to the mapped packet credit register.
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* Host writes number of info/buffer ptrs available to this register
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*/
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void *pkts_credit_reg;
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/** Pointer to the mapped packet sent register. OCTEON TX2 writes the
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* number of packets DMA'ed to host memory in this register.
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*/
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void *pkts_sent_reg;
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/* Statistics for this DROQ. */
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struct sdp_droq_stats stats;
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/* DMA mapped address of the DROQ descriptor ring. */
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size_t desc_ring_dma;
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/* Info_ptr list is allocated at this virtual address. */
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size_t info_base_addr;
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/* DMA mapped address of the info list */
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size_t info_list_dma;
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/* Allocated size of info list. */
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uint32_t info_alloc_size;
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/* Memory zone **/
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const struct rte_memzone *desc_ring_mz;
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const struct rte_memzone *info_mz;
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};
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#define SDP_DROQ_SIZE (sizeof(struct sdp_droq))
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/* IQ/OQ mask */
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struct sdp_io_enable {
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uint64_t iq;
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uint64_t oq;
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uint64_t iq64B;
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};
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/* Structure to define the configuration. */
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struct sdp_config {
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/* Input Queue attributes. */
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struct sdp_iq_config iq;
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/* Output Queue attributes. */
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struct sdp_oq_config oq;
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/* Num of desc for IQ rings */
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uint32_t num_iqdef_descs;
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/* Num of desc for OQ rings */
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uint32_t num_oqdef_descs;
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/* OQ buffer size */
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uint32_t oqdef_buf_size;
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};
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/* Required functions for each VF device */
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struct sdp_fn_list {
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void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
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void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
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int (*setup_device_regs)(struct sdp_device *sdpvf);
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uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
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void (*enable_io_queues)(struct sdp_device *sdpvf);
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void (*disable_io_queues)(struct sdp_device *sdpvf);
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void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
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void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
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void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
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void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
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};
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/* SRIOV information */
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struct sdp_sriov_info {
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/* Number of rings assigned to VF */
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uint32_t rings_per_vf;
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/* Number of VF devices enabled */
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uint32_t num_vfs;
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};
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/* Information to be passed from application */
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struct sdp_rawdev_info {
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struct rte_mempool *enqdeq_mpool;
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const struct sdp_config *app_conf;
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};
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/* SDP EP VF device */
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struct sdp_device {
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/* PCI device pointer */
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struct rte_pci_device *pci_dev;
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uint16_t chip_id;
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uint16_t pf_num;
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uint16_t vf_num;
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/* This device's PCIe port used for traffic. */
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uint16_t pcie_port;
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uint32_t pkind;
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/* The state of this device */
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rte_atomic64_t status;
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/* Memory mapped h/w address */
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uint8_t *hw_addr;
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struct sdp_fn_list fn_list;
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/* Num IQs */
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uint32_t num_iqs;
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/* The input instruction queues */
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struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
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/* Num OQs */
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uint32_t num_oqs;
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/* The DROQ output queues */
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struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
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/* IOQ data buffer pool */
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struct rte_mempool *enqdeq_mpool;
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/* IOQ mask */
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struct sdp_io_enable io_qmask;
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/* SR-IOV info */
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struct sdp_sriov_info sriov_info;
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/* Device configuration */
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const struct sdp_config *conf;
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};
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const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
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int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
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int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
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int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
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int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
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int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
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unsigned int count, rte_rawdev_obj_t context);
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int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
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unsigned int count, rte_rawdev_obj_t context);
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int sdp_rawdev_selftest(uint16_t dev_id);
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#endif /* _OTX2_EP_RAWDEV_H_ */
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