mirror of https://github.com/F-Stack/f-stack.git
175 lines
5.3 KiB
C
175 lines
5.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2019 Intel Corporation
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*/
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#ifndef _OPAE_SPI_H
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#define _OPAE_SPI_H
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#include "opae_osdep.h"
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#define ALTERA_SPI_RXDATA 0
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#define ALTERA_SPI_TXDATA 4
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#define ALTERA_SPI_STATUS 8
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#define ALTERA_SPI_CONTROL 12
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#define ALTERA_SPI_SLAVE_SEL 20
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#define ALTERA_SPI_STATUS_ROE_MSK 0x8
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#define ALTERA_SPI_STATUS_TOE_MSK 0x10
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#define ALTERA_SPI_STATUS_TMT_MSK 0x20
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#define ALTERA_SPI_STATUS_TRDY_MSK 0x40
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#define ALTERA_SPI_STATUS_RRDY_MSK 0x80
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#define ALTERA_SPI_STATUS_E_MSK 0x100
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#define ALTERA_SPI_CONTROL_IROE_MSK 0x8
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#define ALTERA_SPI_CONTROL_ITOE_MSK 0x10
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#define ALTERA_SPI_CONTROL_ITRDY_MSK 0x40
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#define ALTERA_SPI_CONTROL_IRRDY_MSK 0x80
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#define ALTERA_SPI_CONTROL_IE_MSK 0x100
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#define ALTERA_SPI_CONTROL_SSO_MSK 0x400
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#define SPI_CORE_PARAM 0x8
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#define SPI_CTRL 0x10
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#define CTRL_R BIT_ULL(9)
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#define CTRL_W BIT_ULL(8)
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#define CTRL_ADDR_MASK GENMASK_ULL(2, 0)
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#define SPI_READ 0x18
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#define READ_DATA_VALID BIT_ULL(32)
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#define READ_DATA_MASK GENMASK_ULL(31, 0)
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#define SPI_WRITE 0x20
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#define WRITE_DATA_MASK GENMASK_ULL(31, 0)
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#define SPI_MAX_RETRY 1000000
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#define TYPE_SPI 0
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#define TYPE_NIOS_SPI 1
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struct spi_core_param {
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union {
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u64 info;
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struct {
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u8 type:1;
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u8 endian:1;
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u8 data_width:6;
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u8 num_chipselect:6;
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u8 clock_polarity:1;
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u8 clock_phase:1;
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u8 stages:2;
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u8 resvd:4;
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u16 clock:10;
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u16 peripheral_id:16;
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u8 controller_type:1;
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u16 resvd1:15;
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};
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};
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};
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struct altera_spi_device {
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u8 *regs;
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struct spi_core_param spi_param;
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int data_width; /* how many bytes for data width */
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int endian;
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#define SPI_BIG_ENDIAN 0
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#define SPI_LITTLE_ENDIAN 1
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int num_chipselect;
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unsigned char *rxbuf;
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unsigned char *txbuf;
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unsigned int len;
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int (*reg_read)(struct altera_spi_device *dev, u32 reg, u32 *val);
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int (*reg_write)(struct altera_spi_device *dev, u32 reg,
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u32 value);
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/* below are data to be shared in multiple process */
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pthread_mutex_t *mutex; /* to be passed to spi_transaction_dev */
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unsigned int *dtb_sz_ptr; /* to be used in init_max10_device_table */
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unsigned char *dtb; /* to be used in init_max10_device_table */
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};
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#define HEADER_LEN 8
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#define RESPONSE_LEN 4
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#define SPI_TRANSACTION_MAX_LEN 1024
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#define TRAN_SEND_MAX_LEN (SPI_TRANSACTION_MAX_LEN + HEADER_LEN)
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#define TRAN_RESP_MAX_LEN SPI_TRANSACTION_MAX_LEN
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#define PACKET_SEND_MAX_LEN (2*TRAN_SEND_MAX_LEN + 4)
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#define PACKET_RESP_MAX_LEN (2*TRAN_RESP_MAX_LEN + 4)
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#define BYTES_SEND_MAX_LEN (2*PACKET_SEND_MAX_LEN)
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#define BYTES_RESP_MAX_LEN (2*PACKET_RESP_MAX_LEN)
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struct spi_tran_buffer {
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unsigned char tran_send[TRAN_SEND_MAX_LEN];
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unsigned char tran_resp[TRAN_RESP_MAX_LEN];
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unsigned char packet_send[PACKET_SEND_MAX_LEN];
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unsigned char packet_resp[PACKET_RESP_MAX_LEN];
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unsigned char bytes_send[BYTES_SEND_MAX_LEN];
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unsigned char bytes_resp[2*BYTES_RESP_MAX_LEN];
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};
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struct spi_transaction_dev {
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struct altera_spi_device *dev;
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int chipselect;
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struct spi_tran_buffer *buffer;
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pthread_mutex_t lock;
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pthread_mutex_t *mutex; /* multi-process mutex from adapter */
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};
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struct spi_tran_header {
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u8 trans_type;
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u8 reserve;
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u16 size;
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u32 addr;
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};
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int spi_command(struct altera_spi_device *dev, unsigned int chip_select,
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unsigned int wlen, void *wdata, unsigned int rlen, void *rdata);
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void spi_cs_deactivate(struct altera_spi_device *dev);
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void spi_cs_activate(struct altera_spi_device *dev, unsigned int chip_select);
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struct altera_spi_device *altera_spi_alloc(void *base, int type);
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void altera_spi_init(struct altera_spi_device *dev);
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void altera_spi_release(struct altera_spi_device *dev);
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int spi_transaction_read(struct spi_transaction_dev *dev, unsigned int addr,
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unsigned int size, unsigned char *data);
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int spi_transaction_write(struct spi_transaction_dev *dev, unsigned int addr,
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unsigned int size, unsigned char *data);
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struct spi_transaction_dev *spi_transaction_init(struct altera_spi_device *dev,
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int chipselect);
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void spi_transaction_remove(struct spi_transaction_dev *dev);
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int spi_reg_write(struct altera_spi_device *dev, u32 reg,
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u32 value);
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int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);
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#define NIOS_SPI_PARAM 0x8
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#define CONTROL_TYPE BIT_ULL(48)
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#define PERI_ID GENMASK_ULL(47, 32)
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#define SPI_CLK GENMASK_ULL(31, 22)
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#define SYNC_STAGES GENMASK_ULL(17, 16)
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#define CLOCK_PHASE BIT_ULL(15)
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#define CLOCK_POLARITY BIT_ULL(14)
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#define NUM_SELECT GENMASK_ULL(13, 8)
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#define DATA_WIDTH GENMASK_ULL(7, 2)
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#define SHIFT_DIRECTION BIT_ULL(1)
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#define SPI_TYPE BIT_ULL(0)
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#define NIOS_SPI_CTRL 0x10
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#define NIOS_SPI_RD (0x1ULL << 62)
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#define NIOS_SPI_WR (0x2ULL << 62)
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#define NIOS_SPI_COMMAND GENMASK_ULL(63, 62)
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#define NIOS_SPI_ADDR GENMASK_ULL(44, 32)
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#define NIOS_SPI_WRITE_DATA GENMASK_ULL(31, 0)
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#define NIOS_SPI_STAT 0x18
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#define NIOS_SPI_VALID BIT_ULL(32)
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#define NIOS_SPI_READ_DATA GENMASK_ULL(31, 0)
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#define NIOS_INIT 0x1000
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#define REQ_FEC_MODE GENMASK(23, 8)
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#define REQ_FEC_MODE_SHIFT 8
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#define FEC_MODE_NO 0x0
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#define FEC_MODE_KR 0x5555
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#define FEC_MODE_RS 0xaaaa
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#define NIOS_INIT_START BIT(1)
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#define NIOS_INIT_DONE BIT(0)
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#define NIOS_VERSION 0x1004
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#define NIOS_VERSION_MAJOR_SHIFT 28
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#define NIOS_VERSION_MAJOR GENMASK(31, 28)
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#define NIOS_VERSION_MINOR GENMASK(27, 24)
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#define NIOS_VERSION_PATCH GENMASK(23, 20)
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#define PKVL_A_MODE_STS 0x1020
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#define PKVL_B_MODE_STS 0x1024
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#endif
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