mirror of https://github.com/F-Stack/f-stack.git
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Broadcom
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* All rights reserved.
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*/
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#ifndef _BNXT_RXR_H_
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#define _BNXT_RXR_H_
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#include "hsi_struct_def_dpdk.h"
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#define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
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((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
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RX_TPA_START_CMPL_AGG_ID_SFT)
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#define BNXT_TPA_START_AGG_ID_TH(cmp) \
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rte_le_to_cpu_16((cmp)->agg_id)
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static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
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struct rx_tpa_start_cmpl *cmp)
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{
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if (BNXT_CHIP_THOR(bp))
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return BNXT_TPA_START_AGG_ID_TH(cmp);
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else
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return BNXT_TPA_START_AGG_ID_PRE_TH(cmp);
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}
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#define BNXT_TPA_END_AGG_BUFS(cmp) \
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(((cmp)->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) \
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>> RX_TPA_END_CMPL_AGG_BUFS_SFT)
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#define BNXT_TPA_END_AGG_BUFS_TH(cmp) \
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((cmp)->tpa_agg_bufs)
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#define BNXT_TPA_END_AGG_ID(cmp) \
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(((cmp)->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> \
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RX_TPA_END_CMPL_AGG_ID_SFT)
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#define BNXT_TPA_END_AGG_ID_TH(cmp) \
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rte_le_to_cpu_16((cmp)->agg_id)
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#define BNXT_RX_POST_THRESH 32
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/* Number of descriptors to process per inner loop in vector mode. */
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#define RTE_BNXT_DESCS_PER_LOOP 4U
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struct bnxt_tpa_info {
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struct rte_mbuf *mbuf;
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uint16_t len;
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uint32_t agg_count;
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struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
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};
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struct bnxt_rx_ring_info {
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uint16_t rx_prod;
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uint16_t ag_prod;
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uint16_t rx_cons; /* Needed for representor */
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struct bnxt_db_info rx_db;
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struct bnxt_db_info ag_db;
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struct rx_prod_pkt_bd *rx_desc_ring;
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struct rx_prod_pkt_bd *ag_desc_ring;
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struct rte_mbuf **rx_buf_ring; /* sw ring */
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struct rte_mbuf **ag_buf_ring; /* sw ring */
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rte_iova_t rx_desc_mapping;
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rte_iova_t ag_desc_mapping;
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struct bnxt_ring *rx_ring_struct;
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struct bnxt_ring *ag_ring_struct;
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/*
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* To deal with out of order return from TPA, use free buffer indicator
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*/
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struct rte_bitmap *ag_bitmap;
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struct bnxt_tpa_info *tpa_info;
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};
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uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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void bnxt_free_rx_rings(struct bnxt *bp);
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int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
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int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
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int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
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uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
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#endif
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void bnxt_set_mark_in_mbuf(struct bnxt *bp,
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struct rx_pkt_cmpl_hi *rxcmp1,
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struct rte_mbuf *mbuf);
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typedef uint32_t bnxt_cfa_code_dynfield_t;
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extern int bnxt_cfa_code_dynfield_offset;
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static inline bnxt_cfa_code_dynfield_t *
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bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
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{
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return RTE_MBUF_DYNFIELD(mbuf,
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bnxt_cfa_code_dynfield_offset, bnxt_cfa_code_dynfield_t *);
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}
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#define BNXT_RX_META_CFA_CODE_SHIFT 19
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#define BNXT_CFA_CODE_META_SHIFT 16
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#define BNXT_RX_META_CFA_CODE_INT_ACT_REC_BIT 0x8000000
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#define BNXT_RX_META_CFA_CODE_EEM_BIT 0x4000000
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#define BNXT_CFA_META_FMT_MASK 0x70
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#define BNXT_CFA_META_FMT_SHFT 4
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#define BNXT_CFA_META_FMT_EM_EEM_SHFT 1
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#define BNXT_CFA_META_FMT_EEM 3
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#define BNXT_CFA_META_EEM_TCAM_SHIFT 31
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#define BNXT_CFA_META_EM_TEST(x) ((x) >> BNXT_CFA_META_EEM_TCAM_SHIFT)
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#define BNXT_PTYPE_TBL_DIM 128
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extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
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#define BNXT_OL_FLAGS_TBL_DIM 32
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extern uint32_t bnxt_ol_flags_table[BNXT_OL_FLAGS_TBL_DIM];
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#define BNXT_OL_FLAGS_ERR_TBL_DIM 16
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extern uint32_t bnxt_ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM];
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#endif
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