mirror of https://github.com/F-Stack/f-stack.git
438 lines
14 KiB
C
438 lines
14 KiB
C
/*-
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* Copyright (c) 2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _GIC_V3_REG_H_
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#define _GIC_V3_REG_H_
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/*
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* Maximum number of interrupts
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* supported by GIC (including SGIs, PPIs and SPIs)
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*/
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#define GIC_I_NUM_MAX (1020)
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/*
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* Priority MAX/MIN values
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*/
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#define GIC_PRIORITY_MAX (0x00UL)
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/* Upper value is determined by LPI max priority */
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#define GIC_PRIORITY_MIN (0xFCUL)
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/* Numbers for software generated interrupts */
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#define GIC_FIRST_SGI (0)
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#define GIC_LAST_SGI (15)
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/* Numbers for private peripheral interrupts */
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#define GIC_FIRST_PPI (16)
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#define GIC_LAST_PPI (31)
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/* Numbers for spared peripheral interrupts */
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#define GIC_FIRST_SPI (32)
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#define GIC_LAST_SPI (1019)
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/* Numbers for local peripheral interrupts */
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#define GIC_FIRST_LPI (8192)
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/*
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* Registers (v2/v3)
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*/
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#define GICD_CTLR (0x0000)
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#define GICD_CTLR_G1 (1 << 0)
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#define GICD_CTLR_G1A (1 << 1)
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#define GICD_CTLR_ARE_NS (1 << 4)
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#define GICD_CTLR_RWP (1 << 31)
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#define GICD_TYPER (0x0004)
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#define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)
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#define GICD_TYPER_I_NUM(n) ((((n) & 0x1F) + 1) * 32)
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#define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4))
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#define GICD_I_PER_ISENABLERn (32)
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#define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4))
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#define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4))
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#define GICD_I_PER_IPRIORITYn (4)
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#define GICD_I_MASK(n) (1 << ((n) % 32))
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#define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4))
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/* First bit is a polarity bit (0 - low, 1 - high) */
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#define GICD_ICFGR_POL_LOW (0 << 0)
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#define GICD_ICFGR_POL_HIGH (1 << 0)
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#define GICD_ICFGR_POL_MASK (0x1)
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/* Second bit is a trigger bit (0 - level, 1 - edge) */
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#define GICD_ICFGR_TRIG_LVL (0 << 1)
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#define GICD_ICFGR_TRIG_EDGE (1 << 1)
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#define GICD_ICFGR_TRIG_MASK (0x2)
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#define GICD_I_PER_ICFGRn (16)
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/*
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* Registers (v3)
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*/
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#define GICD_IROUTER(n) (0x6000 + ((n) * 8))
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#define GICD_PIDR2 (0xFFE8)
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#define GICR_PIDR2_ARCH_MASK (0xF0)
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#define GICR_PIDR2_ARCH_GICv3 (0x30)
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#define GICR_PIDR2_ARCH_GICv4 (0x40)
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/* Redistributor registers */
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#define GICR_CTLR GICD_CTLR
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#define GICR_CTLR_LPI_ENABLE (1 << 0)
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#define GICR_PIDR2 GICD_PIDR2
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#define GICR_TYPER (0x0008)
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#define GICR_TYPER_PLPIS (1 << 0)
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#define GICR_TYPER_VLPIS (1 << 1)
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#define GICR_TYPER_LAST (1 << 4)
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#define GICR_TYPER_CPUNUM_SHIFT (8)
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#define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT)
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#define GICR_TYPER_CPUNUM(x) \
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(((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT)
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#define GICR_TYPER_AFF_SHIFT (32)
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#define GICR_WAKER (0x0014)
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#define GICR_WAKER_PS (1 << 1) /* Processor sleep */
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#define GICR_WAKER_CA (1 << 2) /* Children asleep */
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#define GICR_PROPBASER (0x0070)
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#define GICR_PROPBASER_IDBITS_MASK 0x1FUL
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/*
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* Cacheability
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* 0x0 - Device-nGnRnE
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* 0x1 - Normal Inner Non-cacheable
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* 0x2 - Normal Inner Read-allocate, Write-through
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* 0x3 - Normal Inner Read-allocate, Write-back
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* 0x4 - Normal Inner Write-allocate, Write-through
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* 0x5 - Normal Inner Write-allocate, Write-back
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* 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
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* 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
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*/
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#define GICR_PROPBASER_CACHE_SHIFT 7
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#define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL
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#define GICR_PROPBASER_CACHE_NIN 0x1UL
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#define GICR_PROPBASER_CACHE_NIRAWT 0x2UL
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#define GICR_PROPBASER_CACHE_NIRAWB 0x3UL
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#define GICR_PROPBASER_CACHE_NIWAWT 0x4UL
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#define GICR_PROPBASER_CACHE_NIWAWB 0x5UL
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#define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL
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#define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL
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#define GICR_PROPBASER_CACHE_MASK \
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(0x7UL << GICR_PROPBASER_CACHE_SHIFT)
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/*
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* Shareability
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* 0x0 - Non-shareable
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* 0x1 - Inner-shareable
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* 0x2 - Outer-shareable
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* 0x3 - Reserved. Threated as 0x0
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*/
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#define GICR_PROPBASER_SHARE_SHIFT 10
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#define GICR_PROPBASER_SHARE_NS 0x0UL
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#define GICR_PROPBASER_SHARE_IS 0x1UL
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#define GICR_PROPBASER_SHARE_OS 0x2UL
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#define GICR_PROPBASER_SHARE_RES 0x3UL
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#define GICR_PROPBASER_SHARE_MASK \
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(0x3UL << GICR_PROPBASER_SHARE_SHIFT)
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#define GICR_PENDBASER (0x0078)
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/*
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* Cacheability
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* 0x0 - Device-nGnRnE
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* 0x1 - Normal Inner Non-cacheable
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* 0x2 - Normal Inner Read-allocate, Write-through
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* 0x3 - Normal Inner Read-allocate, Write-back
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* 0x4 - Normal Inner Write-allocate, Write-through
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* 0x5 - Normal Inner Write-allocate, Write-back
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* 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
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* 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
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*/
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#define GICR_PENDBASER_CACHE_SHIFT 7
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#define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL
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#define GICR_PENDBASER_CACHE_NIN 0x1UL
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#define GICR_PENDBASER_CACHE_NIRAWT 0x2UL
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#define GICR_PENDBASER_CACHE_NIRAWB 0x3UL
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#define GICR_PENDBASER_CACHE_NIWAWT 0x4UL
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#define GICR_PENDBASER_CACHE_NIWAWB 0x5UL
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#define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL
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#define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL
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#define GICR_PENDBASER_CACHE_MASK \
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(0x7UL << GICR_PENDBASER_CACHE_SHIFT)
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/*
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* Shareability
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* 0x0 - Non-shareable
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* 0x1 - Inner-shareable
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* 0x2 - Outer-shareable
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* 0x3 - Reserved. Threated as 0x0
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*/
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#define GICR_PENDBASER_SHARE_SHIFT 10
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#define GICR_PENDBASER_SHARE_NS 0x0UL
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#define GICR_PENDBASER_SHARE_IS 0x1UL
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#define GICR_PENDBASER_SHARE_OS 0x2UL
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#define GICR_PENDBASER_SHARE_RES 0x3UL
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#define GICR_PENDBASER_SHARE_MASK \
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(0x3UL << GICR_PENDBASER_SHARE_SHIFT)
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/* Re-distributor registers for SGIs and PPIs */
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#define GICR_RD_BASE_SIZE PAGE_SIZE_64K
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#define GICR_SGI_BASE_SIZE PAGE_SIZE_64K
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#define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K
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#define GICR_RESERVED_SIZE PAGE_SIZE_64K
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#define GICR_ISENABLER0 (0x0100)
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#define GICR_ICENABLER0 (0x0180)
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#define GICR_I_ENABLER_SGI_MASK (0x0000FFFF)
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#define GICR_I_ENABLER_PPI_MASK (0xFFFF0000)
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#define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn)
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/* ITS registers */
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#define GITS_PIDR2 GICR_PIDR2
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#define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK
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#define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3
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#define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4
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#define GITS_CTLR (0x0000)
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#define GITS_CTLR_EN (1 << 0)
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#define GITS_IIDR (0x0004)
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#define GITS_IIDR_PRODUCT_SHIFT 24
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#define GITS_IIDR_PRODUCT_MASK (0xff << GITS_IIDR_PRODUCT_SHIFT)
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#define GITS_IIDR_VARIANT_SHIFT 16
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#define GITS_IIDR_VARIANT_MASK (0xf << GITS_IIDR_VARIANT_SHIFT)
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#define GITS_IIDR_REVISION_SHIFT 12
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#define GITS_IIDR_REVISION_MASK (0xf << GITS_IIDR_REVISION_SHIFT)
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#define GITS_IIDR_IMPLEMENTOR_SHIFT 0
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#define GITS_IIDR_IMPLEMENTOR_MASK (0xfff << GITS_IIDR_IMPLEMENTOR_SHIFT)
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#define GITS_IIDR_RAW(impl, prod, var, rev) \
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((prod) << GITS_IIDR_PRODUCT_SHIFT | \
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(var) << GITS_IIDR_VARIANT_SHIFT | \
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(rev) << GITS_IIDR_REVISION_SHIFT | \
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(impl) << GITS_IIDR_IMPLEMENTOR_SHIFT)
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#define GITS_IIDR_IMPL_CAVIUM (0x34c)
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#define GITS_IIDR_PROD_THUNDER (0xa1)
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#define GITS_IIDR_VAR_THUNDER_1 (0x0)
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#define GITS_CBASER (0x0080)
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#define GITS_CBASER_VALID (1UL << 63)
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/*
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* Cacheability
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* 0x0 - Device-nGnRnE
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* 0x1 - Normal Inner Non-cacheable
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* 0x2 - Normal Inner Read-allocate, Write-through
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* 0x3 - Normal Inner Read-allocate, Write-back
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* 0x4 - Normal Inner Write-allocate, Write-through
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* 0x5 - Normal Inner Write-allocate, Write-back
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* 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through
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* 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back
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*/
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#define GITS_CBASER_CACHE_SHIFT 59
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#define GITS_CBASER_CACHE_DnGnRnE 0x0UL
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#define GITS_CBASER_CACHE_NIN 0x1UL
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#define GITS_CBASER_CACHE_NIRAWT 0x2UL
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#define GITS_CBASER_CACHE_NIRAWB 0x3UL
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#define GITS_CBASER_CACHE_NIWAWT 0x4UL
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#define GITS_CBASER_CACHE_NIWAWB 0x5UL
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#define GITS_CBASER_CACHE_NIRAWAWT 0x6UL
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#define GITS_CBASER_CACHE_NIRAWAWB 0x7UL
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#define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_CACHE_SHIFT)
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/*
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* Shareability
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* 0x0 - Non-shareable
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* 0x1 - Inner-shareable
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* 0x2 - Outer-shareable
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* 0x3 - Reserved. Threated as 0x0
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*/
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#define GITS_CBASER_SHARE_SHIFT 10
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#define GITS_CBASER_SHARE_NS 0x0UL
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#define GITS_CBASER_SHARE_IS 0x1UL
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#define GITS_CBASER_SHARE_OS 0x2UL
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#define GITS_CBASER_SHARE_RES 0x3UL
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#define GITS_CBASER_SHARE_MASK \
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(0x3UL << GITS_CBASER_SHARE_SHIFT)
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#define GITS_CBASER_PA_SHIFT 12
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#define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT)
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#define GITS_CWRITER (0x0088)
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#define GITS_CREADR (0x0090)
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#define GITS_BASER_BASE (0x0100)
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#define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8)
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#define GITS_BASER_VALID (1UL << 63)
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#define GITS_BASER_TYPE_SHIFT 56
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#define GITS_BASER_TYPE(x) \
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(((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT)
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#define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */
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#define GITS_BASER_TYPE_DEV 0x1UL /* Devices */
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#define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */
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#define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */
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#define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */
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#define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */
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#define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */
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#define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */
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#define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT)
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/*
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* Cacheability
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* 0x0 - Non-cacheable, non-bufferable
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* 0x1 - Non-cacheable
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* 0x2 - Read-allocate, Write-through
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* 0x3 - Read-allocate, Write-back
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* 0x4 - Write-allocate, Write-through
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* 0x5 - Write-allocate, Write-back
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* 0x6 - Read-allocate, Write-allocate, Write-through
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* 0x7 - Read-allocate, Write-allocate, Write-back
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*/
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#define GITS_BASER_CACHE_SHIFT 59
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#define GITS_BASER_CACHE_NCNB 0x0UL
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#define GITS_BASER_CACHE_NC 0x1UL
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#define GITS_BASER_CACHE_RAWT 0x2UL
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#define GITS_BASER_CACHE_RAWB 0x3UL
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#define GITS_BASER_CACHE_WAWT 0x4UL
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#define GITS_BASER_CACHE_WAWB 0x5UL
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#define GITS_BASER_CACHE_RAWAWT 0x6UL
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#define GITS_BASER_CACHE_RAWAWB 0x7UL
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#define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT)
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#define GITS_BASER_ESIZE_SHIFT 48
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#define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT)
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#define GITS_BASER_ESIZE(x) \
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((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1)
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#define GITS_BASER_PA_SHIFT 12
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#define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT)
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/*
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* Shareability
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* 0x0 - Non-shareable
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* 0x1 - Inner-shareable
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* 0x2 - Outer-shareable
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* 0x3 - Reserved. Threated as 0x0
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*/
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#define GITS_BASER_SHARE_SHIFT 10
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#define GITS_BASER_SHARE_NS 0x0UL
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#define GITS_BASER_SHARE_IS 0x1UL
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#define GITS_BASER_SHARE_OS 0x2UL
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#define GITS_BASER_SHARE_RES 0x3UL
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#define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT)
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#define GITS_BASER_PSZ_SHIFT 8
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#define GITS_BASER_PSZ_4K 0x0UL
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#define GITS_BASER_PSZ_16K 0x1UL
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#define GITS_BASER_PSZ_64K 0x2UL
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#define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT)
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#define GITS_BASER_SIZE_MASK 0xFFUL
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#define GITS_BASER_NUM 8
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#define GITS_TYPER (0x0008)
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#define GITS_TYPER_PTA (1UL << 19)
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#define GITS_TYPER_DEVB_SHIFT 13
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#define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT)
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/* Number of device identifiers implemented */
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#define GITS_TYPER_DEVB(x) \
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((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1)
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#define GITS_TYPER_ITTES_SHIFT 4
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#define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT)
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/* Number of bytes per ITT Entry */
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#define GITS_TYPER_ITTES(x) \
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((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1)
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#define GITS_TRANSLATER (0x10040)
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/*
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* LPI related
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*/
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#define LPI_CONF_PRIO_MASK (0xFC)
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#define LPI_CONF_GROUP1 (1 << 1)
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#define LPI_CONF_ENABLE (1 << 0)
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/*
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* CPU interface
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*/
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/*
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* Registers list (ICC_xyz_EL1):
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*
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* PMR - Priority Mask Register
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* * interrupts of priority higher than specified
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* in this mask will be signalled to the CPU.
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* (0xff - lowest possible prio., 0x00 - highest prio.)
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*
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* CTLR - Control Register
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* * controls behavior of the CPU interface and displays
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* implemented features.
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*
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* IGRPEN1 - Interrupt Group 1 Enable Register
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*
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* IAR1 - Interrupt Acknowledge Register Group 1
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* * contains number of the highest priority pending
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* interrupt from the Group 1.
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*
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* EOIR1 - End of Interrupt Register Group 1
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* * Writes inform CPU interface about completed Group 1
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* interrupts processing.
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*/
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|
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#define gic_icc_write(reg, val) \
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do { \
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WRITE_SPECIALREG(ICC_ ##reg ##_EL1, val); \
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isb(); \
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} while (0)
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|
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#define gic_icc_read(reg) \
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({ \
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uint64_t val; \
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|
\
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val = READ_SPECIALREG(ICC_ ##reg ##_EL1); \
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|
(val); \
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|
})
|
|
|
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#define gic_icc_set(reg, mask) \
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|
do { \
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|
uint64_t val; \
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|
val = gic_icc_read(reg); \
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|
val |= (mask); \
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gic_icc_write(reg, val); \
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} while (0)
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|
|
|
#define gic_icc_clear(reg, mask) \
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|
do { \
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|
uint64_t val; \
|
|
val = gic_icc_read(reg); \
|
|
val &= ~(mask); \
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|
gic_icc_write(reg, val); \
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|
} while (0)
|
|
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|
#endif /* _GIC_V3_REG_H_ */
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