mirror of https://github.com/F-Stack/f-stack.git
520 lines
12 KiB
C
520 lines
12 KiB
C
/*-
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Corporation
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/uio_driver.h>
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#include <linux/io.h>
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#include <linux/msi.h>
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#include <linux/version.h>
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#include <linux/slab.h>
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#ifdef CONFIG_XEN_DOM0
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#include <xen/xen.h>
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#endif
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#include <rte_pci_dev_features.h>
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#include "compat.h"
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/**
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* A structure describing the private information for a uio device.
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*/
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struct rte_uio_pci_dev {
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struct uio_info info;
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struct pci_dev *pdev;
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enum rte_intr_mode mode;
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};
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static char *intr_mode;
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static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
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/* sriov sysfs */
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static ssize_t
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show_max_vfs(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
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}
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static ssize_t
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store_max_vfs(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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int err = 0;
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unsigned long max_vfs;
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struct pci_dev *pdev = to_pci_dev(dev);
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if (0 != kstrtoul(buf, 0, &max_vfs))
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return -EINVAL;
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if (0 == max_vfs)
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pci_disable_sriov(pdev);
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else if (0 == pci_num_vf(pdev))
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err = pci_enable_sriov(pdev, max_vfs);
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else /* do nothing if change max_vfs number */
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err = -EINVAL;
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return err ? err : count;
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}
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static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
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static struct attribute *dev_attrs[] = {
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&dev_attr_max_vfs.attr,
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NULL,
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};
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static const struct attribute_group dev_attr_grp = {
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.attrs = dev_attrs,
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};
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/*
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* It masks the msix on/off of generating MSI-X messages.
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*/
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static void
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igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
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{
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u32 mask_bits = desc->masked;
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unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL;
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if (state != 0)
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mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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else
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mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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if (mask_bits != desc->masked) {
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writel(mask_bits, desc->mask_base + offset);
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readl(desc->mask_base);
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desc->masked = mask_bits;
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}
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}
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/**
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* This is the irqcontrol callback to be registered to uio_info.
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* It can be used to disable/enable interrupt from user space processes.
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*
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* @param info
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* pointer to uio_info.
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* @param irq_state
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* state value. 1 to enable interrupt, 0 to disable interrupt.
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*
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* @return
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* - On success, 0.
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* - On failure, a negative value.
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*/
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static int
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igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
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{
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struct rte_uio_pci_dev *udev = info->priv;
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struct pci_dev *pdev = udev->pdev;
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pci_cfg_access_lock(pdev);
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if (udev->mode == RTE_INTR_MODE_LEGACY)
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pci_intx(pdev, !!irq_state);
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else if (udev->mode == RTE_INTR_MODE_MSIX) {
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struct msi_desc *desc;
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0))
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list_for_each_entry(desc, &pdev->msi_list, list)
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igbuio_msix_mask_irq(desc, irq_state);
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#else
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list_for_each_entry(desc, &pdev->dev.msi_list, list)
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igbuio_msix_mask_irq(desc, irq_state);
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#endif
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}
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pci_cfg_access_unlock(pdev);
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return 0;
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}
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/**
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* This is interrupt handler which will check if the interrupt is for the right device.
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* If yes, disable it here and will be enable later.
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*/
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static irqreturn_t
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igbuio_pci_irqhandler(int irq, struct uio_info *info)
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{
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struct rte_uio_pci_dev *udev = info->priv;
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/* Legacy mode need to mask in hardware */
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if (udev->mode == RTE_INTR_MODE_LEGACY &&
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!pci_check_and_mask_intx(udev->pdev))
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return IRQ_NONE;
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/* Message signal mode, no share IRQ and automasked */
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_XEN_DOM0
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static int
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igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
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{
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int idx;
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idx = (int)vma->vm_pgoff;
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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#ifdef HAVE_PTE_MASK_PAGE_IOMAP
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vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
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#endif
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return remap_pfn_range(vma,
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vma->vm_start,
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info->mem[idx].addr >> PAGE_SHIFT,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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/**
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* This is uio device mmap method which will use igbuio mmap for Xen
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* Dom0 environment.
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*/
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static int
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igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
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{
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int idx;
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if (vma->vm_pgoff >= MAX_UIO_MAPS)
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return -EINVAL;
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if (info->mem[vma->vm_pgoff].size == 0)
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return -EINVAL;
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idx = (int)vma->vm_pgoff;
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switch (info->mem[idx].memtype) {
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case UIO_MEM_PHYS:
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return igbuio_dom0_mmap_phys(info, vma);
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case UIO_MEM_LOGICAL:
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case UIO_MEM_VIRTUAL:
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default:
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return -EINVAL;
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}
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}
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#endif
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/* Remap pci resources described by bar #pci_bar in uio resource n. */
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static int
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igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
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int n, int pci_bar, const char *name)
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{
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unsigned long addr, len;
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void *internal_addr;
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if (n >= ARRAY_SIZE(info->mem))
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return -EINVAL;
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addr = pci_resource_start(dev, pci_bar);
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len = pci_resource_len(dev, pci_bar);
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if (addr == 0 || len == 0)
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return -1;
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internal_addr = ioremap(addr, len);
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if (internal_addr == NULL)
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return -1;
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info->mem[n].name = name;
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info->mem[n].addr = addr;
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info->mem[n].internal_addr = internal_addr;
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info->mem[n].size = len;
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info->mem[n].memtype = UIO_MEM_PHYS;
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return 0;
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}
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/* Get pci port io resources described by bar #pci_bar in uio resource n. */
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static int
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igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
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int n, int pci_bar, const char *name)
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{
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unsigned long addr, len;
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if (n >= ARRAY_SIZE(info->port))
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return -EINVAL;
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addr = pci_resource_start(dev, pci_bar);
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len = pci_resource_len(dev, pci_bar);
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if (addr == 0 || len == 0)
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return -EINVAL;
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info->port[n].name = name;
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info->port[n].start = addr;
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info->port[n].size = len;
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info->port[n].porttype = UIO_PORT_X86;
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return 0;
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}
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/* Unmap previously ioremap'd resources */
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static void
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igbuio_pci_release_iomem(struct uio_info *info)
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{
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int i;
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for (i = 0; i < MAX_UIO_MAPS; i++) {
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if (info->mem[i].internal_addr)
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iounmap(info->mem[i].internal_addr);
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}
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}
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static int
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igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
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{
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int i, iom, iop, ret;
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unsigned long flags;
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static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
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"BAR0",
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"BAR1",
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"BAR2",
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"BAR3",
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"BAR4",
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"BAR5",
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};
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iom = 0;
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iop = 0;
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for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
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if (pci_resource_len(dev, i) != 0 &&
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pci_resource_start(dev, i) != 0) {
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flags = pci_resource_flags(dev, i);
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if (flags & IORESOURCE_MEM) {
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ret = igbuio_pci_setup_iomem(dev, info, iom,
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i, bar_names[i]);
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if (ret != 0)
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return ret;
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iom++;
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} else if (flags & IORESOURCE_IO) {
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ret = igbuio_pci_setup_ioport(dev, info, iop,
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i, bar_names[i]);
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if (ret != 0)
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return ret;
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iop++;
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}
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}
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}
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return (iom != 0) ? ret : -ENOENT;
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
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static int __devinit
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#else
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static int
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#endif
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igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct rte_uio_pci_dev *udev;
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struct msix_entry msix_entry;
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int err;
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udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
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if (!udev)
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return -ENOMEM;
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/*
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* enable device: ask low-level code to enable I/O and
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* memory
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*/
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err = pci_enable_device(dev);
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if (err != 0) {
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dev_err(&dev->dev, "Cannot enable PCI device\n");
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goto fail_free;
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}
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/* enable bus mastering on the device */
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pci_set_master(dev);
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/* remap IO memory */
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err = igbuio_setup_bars(dev, &udev->info);
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if (err != 0)
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goto fail_release_iomem;
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/* set 64-bit DMA mask */
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err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
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if (err != 0) {
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dev_err(&dev->dev, "Cannot set DMA mask\n");
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goto fail_release_iomem;
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}
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err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
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if (err != 0) {
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dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
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goto fail_release_iomem;
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}
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/* fill uio infos */
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udev->info.name = "igb_uio";
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udev->info.version = "0.1";
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udev->info.handler = igbuio_pci_irqhandler;
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udev->info.irqcontrol = igbuio_pci_irqcontrol;
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#ifdef CONFIG_XEN_DOM0
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/* check if the driver run on Xen Dom0 */
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if (xen_initial_domain())
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udev->info.mmap = igbuio_dom0_pci_mmap;
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#endif
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udev->info.priv = udev;
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udev->pdev = dev;
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switch (igbuio_intr_mode_preferred) {
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case RTE_INTR_MODE_MSIX:
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/* Only 1 msi-x vector needed */
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msix_entry.entry = 0;
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#ifdef HAVE_PCI_ENABLE_MSIX
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if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
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#else
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if (pci_enable_msix_range(dev, &msix_entry, 1, 1) == 0) {
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#endif
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dev_dbg(&dev->dev, "using MSI-X");
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udev->info.irq = msix_entry.vector;
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udev->mode = RTE_INTR_MODE_MSIX;
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break;
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}
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/* fall back to INTX */
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case RTE_INTR_MODE_LEGACY:
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if (pci_intx_mask_supported(dev)) {
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dev_dbg(&dev->dev, "using INTX");
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udev->info.irq_flags = IRQF_SHARED;
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udev->info.irq = dev->irq;
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udev->mode = RTE_INTR_MODE_LEGACY;
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break;
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}
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dev_notice(&dev->dev, "PCI INTX mask not supported\n");
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/* fall back to no IRQ */
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case RTE_INTR_MODE_NONE:
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udev->mode = RTE_INTR_MODE_NONE;
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udev->info.irq = 0;
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break;
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default:
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dev_err(&dev->dev, "invalid IRQ mode %u",
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igbuio_intr_mode_preferred);
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err = -EINVAL;
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goto fail_release_iomem;
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}
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err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
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if (err != 0)
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goto fail_release_iomem;
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/* register uio driver */
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err = uio_register_device(&dev->dev, &udev->info);
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if (err != 0)
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goto fail_remove_group;
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pci_set_drvdata(dev, udev);
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dev_info(&dev->dev, "uio device registered with irq %lx\n",
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udev->info.irq);
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return 0;
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fail_remove_group:
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sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
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fail_release_iomem:
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igbuio_pci_release_iomem(&udev->info);
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if (udev->mode == RTE_INTR_MODE_MSIX)
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pci_disable_msix(udev->pdev);
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pci_disable_device(dev);
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fail_free:
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kfree(udev);
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return err;
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}
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static void
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igbuio_pci_remove(struct pci_dev *dev)
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{
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struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
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sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
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uio_unregister_device(&udev->info);
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igbuio_pci_release_iomem(&udev->info);
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if (udev->mode == RTE_INTR_MODE_MSIX)
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pci_disable_msix(dev);
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pci_disable_device(dev);
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pci_set_drvdata(dev, NULL);
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kfree(udev);
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}
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static int
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igbuio_config_intr_mode(char *intr_str)
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{
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if (!intr_str) {
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pr_info("Use MSIX interrupt by default\n");
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return 0;
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}
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if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
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igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
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pr_info("Use MSIX interrupt\n");
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} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
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igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
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pr_info("Use legacy interrupt\n");
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} else {
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pr_info("Error: bad parameter - %s\n", intr_str);
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return -EINVAL;
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}
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return 0;
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}
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static struct pci_driver igbuio_pci_driver = {
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.name = "igb_uio",
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.id_table = NULL,
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.probe = igbuio_pci_probe,
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.remove = igbuio_pci_remove,
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};
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static int __init
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igbuio_pci_init_module(void)
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{
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int ret;
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ret = igbuio_config_intr_mode(intr_mode);
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if (ret < 0)
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return ret;
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return pci_register_driver(&igbuio_pci_driver);
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}
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static void __exit
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igbuio_pci_exit_module(void)
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{
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pci_unregister_driver(&igbuio_pci_driver);
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}
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module_init(igbuio_pci_init_module);
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module_exit(igbuio_pci_exit_module);
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module_param(intr_mode, charp, S_IRUGO);
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MODULE_PARM_DESC(intr_mode,
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"igb_uio interrupt mode (default=msix):\n"
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" " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
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" " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
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"\n");
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MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Intel Corporation");
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