mirror of https://github.com/F-Stack/f-stack.git
111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017-2022 Intel Corporation
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*/
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#include <rte_cryptodev.h>
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#include <cryptodev_pmd.h>
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#include "qat_asym.h"
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#include "qat_crypto.h"
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#include "qat_crypto_pmd_gens.h"
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struct rte_cryptodev_ops qat_asym_crypto_ops_gen1 = {
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/* Device related operations */
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.dev_configure = qat_cryptodev_config,
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.dev_start = qat_cryptodev_start,
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.dev_stop = qat_cryptodev_stop,
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.dev_close = qat_cryptodev_close,
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.dev_infos_get = qat_cryptodev_info_get,
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.stats_get = qat_cryptodev_stats_get,
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.stats_reset = qat_cryptodev_stats_reset,
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.queue_pair_setup = qat_cryptodev_qp_setup,
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.queue_pair_release = qat_cryptodev_qp_release,
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/* Crypto related operations */
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.asym_session_get_size = qat_asym_session_get_private_size,
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.asym_session_configure = qat_asym_session_configure,
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.asym_session_clear = qat_asym_session_clear
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};
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static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {
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QAT_ASYM_CAP(MODEX,
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0, 1, 512, 1),
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QAT_ASYM_CAP(MODINV,
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0, 1, 512, 1),
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QAT_ASYM_CAP(RSA,
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((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
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(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
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(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
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(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
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64, 512, 64),
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RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
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};
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int
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qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,
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const char *capa_memz_name,
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const uint16_t __rte_unused slice_map)
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{
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const uint32_t size = sizeof(qat_asym_crypto_caps_gen1);
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uint32_t i;
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internals->capa_mz = rte_memzone_lookup(capa_memz_name);
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if (internals->capa_mz == NULL) {
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internals->capa_mz = rte_memzone_reserve(capa_memz_name,
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size, rte_socket_id(), 0);
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if (internals->capa_mz == NULL) {
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QAT_LOG(DEBUG,
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"Error allocating memzone for capabilities");
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return -1;
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}
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}
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struct rte_cryptodev_capabilities *addr =
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(struct rte_cryptodev_capabilities *)
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internals->capa_mz->addr;
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const struct rte_cryptodev_capabilities *capabilities =
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qat_asym_crypto_caps_gen1;
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const uint32_t capa_num =
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size / sizeof(struct rte_cryptodev_capabilities);
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uint32_t curr_capa = 0;
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for (i = 0; i < capa_num; i++) {
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memcpy(addr + curr_capa, capabilities + i,
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sizeof(struct rte_cryptodev_capabilities));
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curr_capa++;
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}
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internals->qat_dev_capabilities = internals->capa_mz->addr;
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return 0;
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}
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uint64_t
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qat_asym_crypto_feature_flags_get_gen1(
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struct qat_pci_device *qat_dev __rte_unused)
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{
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uint64_t feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
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RTE_CRYPTODEV_FF_HW_ACCELERATED |
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RTE_CRYPTODEV_FF_ASYM_SESSIONLESS |
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RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP |
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RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
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return feature_flags;
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}
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int
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qat_asym_crypto_set_session_gen1(void *cdev __rte_unused,
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void *session __rte_unused)
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{
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return 0;
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}
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RTE_INIT(qat_asym_crypto_gen1_init)
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{
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qat_asym_gen_dev_ops[QAT_GEN1].cryptodev_ops =
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&qat_asym_crypto_ops_gen1;
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qat_asym_gen_dev_ops[QAT_GEN1].get_capabilities =
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qat_asym_crypto_cap_get_gen1;
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qat_asym_gen_dev_ops[QAT_GEN1].get_feature_flags =
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qat_asym_crypto_feature_flags_get_gen1;
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}
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