mirror of https://github.com/F-Stack/f-stack.git
254 lines
7.1 KiB
C
254 lines
7.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2022 NVIDIA Corporation & Affiliates
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*/
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#ifndef MLX5DR_ACTION_H_
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#define MLX5DR_ACTION_H_
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/* Max number of STEs needed for a rule (including match) */
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#define MLX5DR_ACTION_MAX_STE 10
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enum mlx5dr_action_stc_idx {
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MLX5DR_ACTION_STC_IDX_CTRL = 0,
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MLX5DR_ACTION_STC_IDX_HIT = 1,
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MLX5DR_ACTION_STC_IDX_DW5 = 2,
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MLX5DR_ACTION_STC_IDX_DW6 = 3,
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MLX5DR_ACTION_STC_IDX_DW7 = 4,
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MLX5DR_ACTION_STC_IDX_MAX = 5,
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/* STC Jumvo STE combo: CTR, Hit */
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MLX5DR_ACTION_STC_IDX_LAST_JUMBO_STE = 1,
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/* STC combo1: CTR, SINGLE, DOUBLE, Hit */
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MLX5DR_ACTION_STC_IDX_LAST_COMBO1 = 3,
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/* STC combo2: CTR, 3 x SINGLE, Hit */
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MLX5DR_ACTION_STC_IDX_LAST_COMBO2 = 4,
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};
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enum mlx5dr_action_offset {
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MLX5DR_ACTION_OFFSET_DW0 = 0,
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MLX5DR_ACTION_OFFSET_DW5 = 5,
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MLX5DR_ACTION_OFFSET_DW6 = 6,
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MLX5DR_ACTION_OFFSET_DW7 = 7,
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MLX5DR_ACTION_OFFSET_HIT = 3,
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MLX5DR_ACTION_OFFSET_HIT_LSB = 4,
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};
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enum {
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MLX5DR_ACTION_DOUBLE_SIZE = 8,
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MLX5DR_ACTION_INLINE_DATA_SIZE = 4,
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MLX5DR_ACTION_HDR_LEN_L2_MACS = 12,
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MLX5DR_ACTION_HDR_LEN_L2_VLAN = 4,
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MLX5DR_ACTION_HDR_LEN_L2_ETHER = 2,
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MLX5DR_ACTION_HDR_LEN_L2 = (MLX5DR_ACTION_HDR_LEN_L2_MACS +
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MLX5DR_ACTION_HDR_LEN_L2_ETHER),
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MLX5DR_ACTION_HDR_LEN_L2_W_VLAN = (MLX5DR_ACTION_HDR_LEN_L2 +
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MLX5DR_ACTION_HDR_LEN_L2_VLAN),
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MLX5DR_ACTION_REFORMAT_DATA_SIZE = 64,
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DECAP_L3_NUM_ACTIONS_W_NO_VLAN = 6,
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DECAP_L3_NUM_ACTIONS_W_VLAN = 7,
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};
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enum mlx5dr_action_setter_flag {
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ASF_SINGLE1 = 1 << 0,
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ASF_SINGLE2 = 1 << 1,
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ASF_SINGLE3 = 1 << 2,
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ASF_DOUBLE = ASF_SINGLE2 | ASF_SINGLE3,
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ASF_REPARSE = 1 << 3,
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ASF_REMOVE = 1 << 4,
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ASF_MODIFY = 1 << 5,
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ASF_CTR = 1 << 6,
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ASF_HIT = 1 << 7,
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};
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struct mlx5dr_action_default_stc {
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struct mlx5dr_pool_chunk nop_ctr;
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struct mlx5dr_pool_chunk nop_dw5;
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struct mlx5dr_pool_chunk nop_dw6;
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struct mlx5dr_pool_chunk nop_dw7;
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struct mlx5dr_pool_chunk default_hit;
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uint32_t refcount;
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};
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struct mlx5dr_action_shared_stc {
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struct mlx5dr_pool_chunk remove_header;
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uint32_t refcount;
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};
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struct mlx5dr_actions_apply_data {
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struct mlx5dr_send_engine *queue;
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struct mlx5dr_rule_action *rule_action;
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uint32_t *wqe_data;
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struct mlx5dr_wqe_gta_ctrl_seg *wqe_ctrl;
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uint32_t jump_to_action_stc;
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struct mlx5dr_context_common_res *common_res;
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enum mlx5dr_table_type tbl_type;
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uint32_t next_direct_idx;
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uint8_t require_dep;
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};
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struct mlx5dr_actions_wqe_setter;
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typedef void (*mlx5dr_action_setter_fp)
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(struct mlx5dr_actions_apply_data *apply,
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struct mlx5dr_actions_wqe_setter *setter);
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struct mlx5dr_actions_wqe_setter {
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mlx5dr_action_setter_fp set_single;
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mlx5dr_action_setter_fp set_double;
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mlx5dr_action_setter_fp set_hit;
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mlx5dr_action_setter_fp set_ctr;
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uint8_t idx_single;
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uint8_t idx_double;
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uint8_t idx_ctr;
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uint8_t idx_hit;
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uint8_t flags;
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};
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struct mlx5dr_action_template {
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struct mlx5dr_actions_wqe_setter setters[MLX5DR_ACTION_MAX_STE];
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enum mlx5dr_action_type *action_type_arr;
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uint8_t num_of_action_stes;
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uint8_t num_actions;
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uint8_t only_term;
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};
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struct mlx5dr_action {
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uint8_t type;
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uint8_t flags;
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struct mlx5dr_context *ctx;
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union {
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struct {
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struct mlx5dr_pool_chunk stc[MLX5DR_TABLE_TYPE_MAX];
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union {
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struct {
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struct mlx5dr_devx_obj *pattern_obj;
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struct mlx5dr_devx_obj *arg_obj;
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__be64 single_action;
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uint8_t single_action_type;
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uint16_t num_of_actions;
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} modify_header;
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struct {
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struct mlx5dr_devx_obj *arg_obj;
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uint32_t header_size;
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} reformat;
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struct {
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struct mlx5dr_devx_obj *devx_obj;
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uint8_t return_reg_id;
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} aso;
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struct {
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uint16_t vport_num;
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uint16_t esw_owner_vhca_id;
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} vport;
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};
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};
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struct ibv_flow_action *flow_action;
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struct mlx5dv_devx_obj *devx_obj;
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struct ibv_qp *qp;
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};
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};
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int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[],
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uint32_t num_actions,
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struct mlx5dv_flow_action_attr *attr);
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int mlx5dr_action_get_default_stc(struct mlx5dr_context *ctx,
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uint8_t tbl_type);
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void mlx5dr_action_put_default_stc(struct mlx5dr_context *ctx,
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uint8_t tbl_type);
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void mlx5dr_action_prepare_decap_l3_data(uint8_t *src, uint8_t *dst,
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uint16_t num_of_actions);
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int mlx5dr_action_template_process(struct mlx5dr_action_template *at);
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bool mlx5dr_action_check_combo(enum mlx5dr_action_type *user_actions,
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enum mlx5dr_table_type table_type);
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int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,
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struct mlx5dr_cmd_stc_modify_attr *stc_attr,
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uint32_t table_type,
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struct mlx5dr_pool_chunk *stc);
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void mlx5dr_action_free_single_stc(struct mlx5dr_context *ctx,
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uint32_t table_type,
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struct mlx5dr_pool_chunk *stc);
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static inline void
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mlx5dr_action_setter_default_single(struct mlx5dr_actions_apply_data *apply,
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__rte_unused struct mlx5dr_actions_wqe_setter *setter)
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{
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW5] = 0;
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_DW5] =
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htobe32(apply->common_res->default_stc->nop_dw5.offset);
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}
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static inline void
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mlx5dr_action_setter_default_double(struct mlx5dr_actions_apply_data *apply,
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__rte_unused struct mlx5dr_actions_wqe_setter *setter)
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{
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW6] = 0;
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW7] = 0;
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_DW6] =
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htobe32(apply->common_res->default_stc->nop_dw6.offset);
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_DW7] =
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htobe32(apply->common_res->default_stc->nop_dw7.offset);
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}
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static inline void
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mlx5dr_action_setter_default_ctr(struct mlx5dr_actions_apply_data *apply,
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__rte_unused struct mlx5dr_actions_wqe_setter *setter)
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{
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW0] = 0;
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_CTRL] =
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htobe32(apply->common_res->default_stc->nop_ctr.offset);
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}
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static inline void
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mlx5dr_action_apply_setter(struct mlx5dr_actions_apply_data *apply,
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struct mlx5dr_actions_wqe_setter *setter,
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bool is_jumbo)
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{
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uint8_t num_of_actions;
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/* Set control counter */
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if (setter->flags & ASF_CTR)
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setter->set_ctr(apply, setter);
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else
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mlx5dr_action_setter_default_ctr(apply, setter);
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/* Set single and double on match */
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if (!is_jumbo) {
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if (setter->flags & ASF_SINGLE1)
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setter->set_single(apply, setter);
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else
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mlx5dr_action_setter_default_single(apply, setter);
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if (setter->flags & ASF_DOUBLE)
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setter->set_double(apply, setter);
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else
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mlx5dr_action_setter_default_double(apply, setter);
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num_of_actions = setter->flags & ASF_DOUBLE ?
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MLX5DR_ACTION_STC_IDX_LAST_COMBO1 :
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MLX5DR_ACTION_STC_IDX_LAST_COMBO2;
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} else {
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW5] = 0;
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW6] = 0;
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apply->wqe_data[MLX5DR_ACTION_OFFSET_DW7] = 0;
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_DW5] = 0;
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_DW6] = 0;
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_DW7] = 0;
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num_of_actions = MLX5DR_ACTION_STC_IDX_LAST_JUMBO_STE;
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}
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/* Set next/final hit action */
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setter->set_hit(apply, setter);
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/* Set number of actions */
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apply->wqe_ctrl->stc_ix[MLX5DR_ACTION_STC_IDX_CTRL] |=
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htobe32(num_of_actions << 29);
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}
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#endif /* MLX5DR_ACTION_H_ */
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