mirror of https://github.com/F-Stack/f-stack.git
604 lines
15 KiB
C
604 lines
15 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#include "phy_if.h"
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#define XUSB_PADCTL_USB2_PAD_MUX 0x004
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#define XUSB_PADCTL_ELPG_PROGRAM 0x01C
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#define ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
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#define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
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#define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
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#define IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
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#define IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf<< 12)
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#define IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
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#define IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
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#define IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
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#define IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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#define XUSB_PADCTL_USB3_PAD_MUX 0x134
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
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#define IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
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#define IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
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#define IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
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#define IOPHY_PLL_S0_CTL1_PLL_RST_L (1 << 1)
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#define IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13C
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL4 0x144
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
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#define IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
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#define IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14C
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3 0x150
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4 0x154
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15C
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struct lane_cfg {
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char *function;
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char **lanes;
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int iddq;
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};
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struct xusbpadctl_softc {
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device_t dev;
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struct resource *mem_res;
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hwreset_t rst;
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int phy_ena_cnt;
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};
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-xusb-padctl", 1},
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{NULL, 0},
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};
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struct padctl_lane {
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const char *name;
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bus_size_t reg;
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uint32_t shift;
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uint32_t mask;
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int iddq;
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char **mux;
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int nmux;
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};
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static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"};
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static char *usb_mux[] = {"snps", "xusb"};
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static char *pci_mux[] = {"pcie", "usb3", "sata", "rsvd"};
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#define LANE(n, r, s, m, i, mx) \
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{ \
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.name = n, \
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.reg = r, \
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.shift = s, \
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.mask = m, \
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.iddq = i, \
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.mux = mx, \
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.nmux = nitems(mx), \
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}
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static const struct padctl_lane lanes_tbl[] = {
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LANE("otg-0", XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, -1, otg_mux),
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LANE("otg-1", XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, -1, otg_mux),
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LANE("otg-2", XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, -1, otg_mux),
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LANE("ulpi-0", XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, -1, usb_mux),
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LANE("hsic-0", XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, -1, usb_mux),
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LANE("hsic-1", XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, -1, usb_mux),
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LANE("pcie-0", XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, 1, pci_mux),
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LANE("pcie-1", XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, 2, pci_mux),
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LANE("pcie-2", XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, 3, pci_mux),
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LANE("pcie-3", XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, 4, pci_mux),
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LANE("pcie-4", XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, 5, pci_mux),
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LANE("sata-0", XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, 6, pci_mux),
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};
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static int
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xusbpadctl_mux_function(const struct padctl_lane *lane, char *fnc_name)
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{
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int i;
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for (i = 0; i < lane->nmux; i++) {
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if (strcmp(fnc_name, lane->mux[i]) == 0)
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return (i);
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}
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return (-1);
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}
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static int
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xusbpadctl_config_lane(struct xusbpadctl_softc *sc, char *lane_name,
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const struct padctl_lane *lane, struct lane_cfg *cfg)
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{
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int tmp;
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uint32_t reg;
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reg = bus_read_4(sc->mem_res, lane->reg);
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if (cfg->function != NULL) {
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tmp = xusbpadctl_mux_function(lane, cfg->function);
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if (tmp == -1) {
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device_printf(sc->dev,
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"Unknown function %s for lane %s\n", cfg->function,
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lane_name);
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return (EINVAL);
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}
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reg &= ~(lane->mask << lane->shift);
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reg |= (tmp & lane->mask) << lane->shift;
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}
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if (cfg->iddq != -1) {
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if (lane->iddq == -1) {
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device_printf(sc->dev, "Invalid IDDQ for lane %s\n",
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lane_name);
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return (EINVAL);
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}
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if (cfg->iddq != 0)
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reg &= ~(1 << lane->iddq);
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else
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reg |= 1 << lane->iddq;
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}
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bus_write_4(sc->mem_res, lane->reg, reg);
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return (0);
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}
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static const struct padctl_lane *
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xusbpadctl_search_lane(char *lane_name)
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{
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int i;
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for (i = 0; i < nitems(lanes_tbl); i++) {
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if (strcmp(lane_name, lanes_tbl[i].name) == 0)
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return (&lanes_tbl[i]);
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}
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return (NULL);
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}
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static int
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xusbpadctl_config_node(struct xusbpadctl_softc *sc, char *lane_name,
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struct lane_cfg *cfg)
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{
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const struct padctl_lane *lane;
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int rv;
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lane = xusbpadctl_search_lane(lane_name);
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if (lane == NULL) {
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device_printf(sc->dev, "Unknown lane: %s\n", lane_name);
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return (ENXIO);
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}
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rv = xusbpadctl_config_lane(sc, lane_name, lane, cfg);
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return (rv);
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}
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static int
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xusbpadctl_read_node(struct xusbpadctl_softc *sc, phandle_t node,
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struct lane_cfg *cfg, char **lanes, int *llanes)
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{
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int rv;
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*llanes = OF_getprop_alloc(node, "nvidia,lanes", 1, (void **)lanes);
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if (*llanes <= 0)
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return (ENOENT);
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/* Read function (mux) settings. */
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rv = OF_getprop_alloc(node, "nvidia,function", 1,
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(void **)&cfg->function);
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if (rv <= 0)
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cfg->function = NULL;
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/* Read numeric properties. */
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rv = OF_getencprop(node, "nvidia,iddq", &cfg->iddq,
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sizeof(cfg->iddq));
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if (rv <= 0)
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cfg->iddq = -1;
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return (0);
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}
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static int
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xusbpadctl_process_node(struct xusbpadctl_softc *sc, phandle_t node)
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{
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struct lane_cfg cfg;
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char *lanes, *lname;
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int i, len, llanes, rv;
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rv = xusbpadctl_read_node(sc, node, &cfg, &lanes, &llanes);
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if (rv != 0)
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return (rv);
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len = 0;
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lname = lanes;
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do {
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i = strlen(lname) + 1;
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rv = xusbpadctl_config_node(sc, lname, &cfg);
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if (rv != 0)
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device_printf(sc->dev,
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"Cannot configure lane: %s: %d\n", lname, rv);
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len += i;
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lname += i;
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} while (len < llanes);
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if (lanes != NULL)
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OF_prop_free(lanes);
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if (cfg.function != NULL)
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OF_prop_free(cfg.function);
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return (rv);
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}
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static int
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xusbpadctl_pinctrl_cfg(device_t dev, phandle_t cfgxref)
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{
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struct xusbpadctl_softc *sc;
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phandle_t node, cfgnode;
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int rv;
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sc = device_get_softc(dev);
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cfgnode = OF_node_from_xref(cfgxref);
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rv = 0;
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for (node = OF_child(cfgnode); node != 0; node = OF_peer(node)) {
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if (!fdt_is_enabled(node))
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continue;
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rv = xusbpadctl_process_node(sc, node);
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if (rv != 0)
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return (rv);
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}
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return (rv);
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}
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static int
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xusbpadctl_phy_pcie_powerup(struct xusbpadctl_softc *sc)
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{
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uint32_t reg;
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int i;
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN;
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reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN;
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reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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reg |= IOPHY_PLL_P0_CTL1_PLL_RST;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
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DELAY(100);
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for (i = 0; i < 100; i++) {
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET)
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return (0);
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DELAY(10);
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}
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return (ETIMEDOUT);
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}
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static int
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xusbpadctl_phy_pcie_powerdown(struct xusbpadctl_softc *sc)
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{
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uint32_t reg;
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
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DELAY(100);
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return (0);
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}
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static int
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xusbpadctl_phy_sata_powerup(struct xusbpadctl_softc *sc)
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{
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uint32_t reg;
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int i;
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
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for (i = 100; i >= 0; i--) {
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
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break;
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DELAY(100);
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}
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if (i <= 0) {
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device_printf(sc->dev, "Failed to power up SATA phy\n");
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return (ETIMEDOUT);
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}
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return (0);
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}
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static int
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xusbpadctl_phy_sata_powerdown(struct xusbpadctl_softc *sc)
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{
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uint32_t reg;
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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bus_write_4(sc->mem_res, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
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DELAY(100);
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return (0);
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}
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static int
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xusbpadctl_phy_powerup(struct xusbpadctl_softc *sc)
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{
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uint32_t reg;
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM);
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reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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bus_write_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM);
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reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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bus_write_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM, reg);
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DELAY(100);
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reg = bus_read_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM);
|
|
reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
|
|
bus_write_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM, reg);
|
|
DELAY(100);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xusbpadctl_phy_powerdown(struct xusbpadctl_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = bus_read_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM);
|
|
reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
|
|
bus_write_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM, reg);
|
|
DELAY(100);
|
|
|
|
reg = bus_read_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM);
|
|
reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
|
|
bus_write_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM, reg);
|
|
DELAY(100);
|
|
|
|
reg = bus_read_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM);
|
|
reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
|
|
bus_write_4(sc->mem_res, XUSB_PADCTL_ELPG_PROGRAM, reg);
|
|
DELAY(100);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xusbpadctl_phy_enable(device_t dev, intptr_t id, bool enable)
|
|
{
|
|
struct xusbpadctl_softc *sc;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if ((id != TEGRA_XUSB_PADCTL_PCIE) &&
|
|
(id != TEGRA_XUSB_PADCTL_SATA)) {
|
|
device_printf(dev, "Unknown phy: %d\n", id);
|
|
return (ENXIO);
|
|
}
|
|
|
|
rv = 0;
|
|
if (enable) {
|
|
if (sc->phy_ena_cnt == 0) {
|
|
rv = xusbpadctl_phy_powerup(sc);
|
|
if (rv != 0)
|
|
return (rv);
|
|
}
|
|
sc->phy_ena_cnt++;
|
|
}
|
|
|
|
if (id == TEGRA_XUSB_PADCTL_PCIE) {
|
|
if (enable)
|
|
rv = xusbpadctl_phy_pcie_powerup(sc);
|
|
else
|
|
rv = xusbpadctl_phy_pcie_powerdown(sc);
|
|
if (rv != 0)
|
|
return (rv);
|
|
} else if (id == TEGRA_XUSB_PADCTL_SATA) {
|
|
if (enable)
|
|
rv = xusbpadctl_phy_sata_powerup(sc);
|
|
else
|
|
rv = xusbpadctl_phy_sata_powerdown(sc);
|
|
if (rv != 0)
|
|
return (rv);
|
|
}
|
|
if (!enable) {
|
|
if (sc->phy_ena_cnt == 1) {
|
|
rv = xusbpadctl_phy_powerdown(sc);
|
|
if (rv != 0)
|
|
return (rv);
|
|
}
|
|
sc->phy_ena_cnt--;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xusbpadctl_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Tegra XUSB phy");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
xusbpadctl_detach(device_t dev)
|
|
{
|
|
|
|
/* This device is always present. */
|
|
return (EBUSY);
|
|
}
|
|
|
|
static int
|
|
xusbpadctl_attach(device_t dev)
|
|
{
|
|
struct xusbpadctl_softc * sc;
|
|
int rid, rv;
|
|
phandle_t node;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->mem_res == NULL) {
|
|
device_printf(dev, "Cannot allocate memory resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
node = ofw_bus_get_node(dev);
|
|
rv = hwreset_get_by_ofw_name(dev, "padctl", &sc->rst);
|
|
if (rv != 0) {
|
|
device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
|
|
return (rv);
|
|
}
|
|
rv = hwreset_deassert(sc->rst);
|
|
if (rv != 0) {
|
|
device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
|
|
return (rv);
|
|
}
|
|
|
|
/* Register as a pinctrl device and use default configuration */
|
|
fdt_pinctrl_register(dev, NULL);
|
|
fdt_pinctrl_configure_by_name(dev, "default");
|
|
phy_register_provider(dev);
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
static device_method_t tegra_xusbpadctl_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, xusbpadctl_probe),
|
|
DEVMETHOD(device_attach, xusbpadctl_attach),
|
|
DEVMETHOD(device_detach, xusbpadctl_detach),
|
|
|
|
/* fdt_pinctrl interface */
|
|
DEVMETHOD(fdt_pinctrl_configure, xusbpadctl_pinctrl_cfg),
|
|
|
|
/* phy interface */
|
|
DEVMETHOD(phy_enable, xusbpadctl_phy_enable),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t tegra_xusbpadctl_driver = {
|
|
"tegra_xusbpadctl",
|
|
tegra_xusbpadctl_methods,
|
|
sizeof(struct xusbpadctl_softc),
|
|
};
|
|
|
|
static devclass_t tegra_xusbpadctl_devclass;
|
|
|
|
EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
|
|
tegra_xusbpadctl_devclass, 0, 0, 73);
|