mirror of https://github.com/F-Stack/f-stack.git
787 lines
20 KiB
C
787 lines
20 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <arm64/rockchip/clk/rk_clk_pll.h>
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#include "clkdev_if.h"
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struct rk_clk_pll_sc {
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uint32_t base_offset;
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uint32_t gate_offset;
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uint32_t gate_shift;
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uint32_t mode_reg;
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uint32_t mode_shift;
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uint32_t flags;
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struct rk_clk_pll_rate *rates;
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struct rk_clk_pll_rate *frac_rates;
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};
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#define WRITE4(_clk, off, val) \
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CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
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#define READ4(_clk, off, val) \
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CLKDEV_READ_4(clknode_get_device(_clk), off, val)
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#define DEVICE_LOCK(_clk) \
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CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
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#define DEVICE_UNLOCK(_clk) \
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
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#define RK_CLK_PLL_MASK_SHIFT 16
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#if 0
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#define dprintf(format, arg...) \
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printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
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#else
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#define dprintf(format, arg...)
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#endif
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static int
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rk_clk_pll_set_gate(struct clknode *clk, bool enable)
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{
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struct rk_clk_pll_sc *sc;
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uint32_t val = 0;
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sc = clknode_get_softc(clk);
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if ((sc->flags & RK_CLK_PLL_HAVE_GATE) == 0)
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return (0);
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dprintf("%sabling gate\n", enable ? "En" : "Dis");
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if (!enable)
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val |= 1 << sc->gate_shift;
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dprintf("sc->gate_shift: %x\n", sc->gate_shift);
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val |= (1 << sc->gate_shift) << RK_CLK_PLL_MASK_SHIFT;
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dprintf("Write: gate_offset=%x, val=%x\n", sc->gate_offset, val);
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DEVICE_LOCK(clk);
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WRITE4(clk, sc->gate_offset, val);
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DEVICE_UNLOCK(clk);
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return (0);
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}
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/* CON0 */
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#define RK3066_CLK_PLL_REFDIV_SHIFT 8
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#define RK3066_CLK_PLL_REFDIV_MASK 0x3F00
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#define RK3066_CLK_PLL_POSTDIV_SHIFT 0
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#define RK3066_CLK_PLL_POSTDIV_MASK 0x000F
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/* CON1 */
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#define RK3066_CLK_PLL_LOCK_MASK (1U << 31)
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#define RK3066_CLK_PLL_FBDIV_SHIFT 0
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#define RK3066_CLK_PLL_FBDIV_MASK 0x0FFF
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/* CON2 */
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/* CON3 */
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#define RK3066_CLK_PLL_RESET (1 << 5)
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#define RK3066_CLK_PLL_TEST (1 << 4)
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#define RK3066_CLK_PLL_ENSAT (1 << 3)
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#define RK3066_CLK_PLL_FASTEN (1 << 2)
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#define RK3066_CLK_PLL_POWER_DOWN (1 << 1)
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#define RK3066_CLK_PLL_BYPASS (1 << 0)
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#define RK3066_CLK_PLL_MODE_SLOW 0
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#define RK3066_CLK_PLL_MODE_NORMAL 1
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#define RK3066_CLK_PLL_MODE_DEEP_SLOW 2
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#define RK3066_CLK_PLL_MODE_MASK 0x3
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static int
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rk3066_clk_pll_init(struct clknode *clk, device_t dev)
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{
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struct rk_clk_pll_sc *sc;
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uint32_t reg;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->mode_reg, ®);
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DEVICE_UNLOCK(clk);
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reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK;
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clknode_init_parent_idx(clk, reg);
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return (0);
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}
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static int
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rk3066_clk_pll_set_mux(struct clknode *clk, int idx)
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{
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uint32_t reg;
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struct rk_clk_pll_sc *sc;
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sc = clknode_get_softc(clk);
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reg = (idx & RK3066_CLK_PLL_MODE_MASK) << sc->mode_shift;
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reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) <<
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RK_CLK_PLL_MASK_SHIFT;
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DEVICE_LOCK(clk);
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WRITE4(clk, sc->mode_reg, reg);
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DEVICE_UNLOCK(clk);
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return(0);
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}
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static int
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rk3066_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct rk_clk_pll_sc *sc;
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uint64_t rate;
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uint32_t refdiv, fbdiv, postdiv;
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uint32_t raw0, raw1, raw2, reg;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->base_offset, &raw0);
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READ4(clk, sc->base_offset + 4, &raw1);
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READ4(clk, sc->base_offset + 8, &raw2);
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READ4(clk, sc->mode_reg, ®);
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DEVICE_UNLOCK(clk);
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reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK;
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if (reg != RK3066_CLK_PLL_MODE_NORMAL)
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return (0);
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if (!(raw1 & RK3066_CLK_PLL_LOCK_MASK)) {
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*freq = 0;
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return (0);
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}
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/* TODO MUX */
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refdiv = (raw0 & RK3066_CLK_PLL_REFDIV_MASK) >>
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RK3066_CLK_PLL_REFDIV_SHIFT;
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refdiv += 1;
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postdiv = (raw0 & RK3066_CLK_PLL_POSTDIV_MASK) >>
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RK3066_CLK_PLL_POSTDIV_SHIFT;
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postdiv += 1;
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fbdiv = (raw1 & RK3066_CLK_PLL_FBDIV_MASK) >>
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RK3066_CLK_PLL_FBDIV_SHIFT;
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fbdiv += 1;
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rate = *freq * fbdiv;
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rate /= refdiv;
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*freq = rate / postdiv;
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return (0);
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}
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static int
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rk3066_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
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int flags, int *stop)
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{
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struct rk_clk_pll_rate *rates;
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struct rk_clk_pll_sc *sc;
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uint32_t reg;
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int rv, timeout;
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sc = clknode_get_softc(clk);
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if (sc->rates == NULL)
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return (EINVAL);
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for (rates = sc->rates; rates->freq; rates++) {
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if (rates->freq == *fout)
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break;
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}
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if (rates->freq == 0) {
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*stop = 1;
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return (EINVAL);
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}
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DEVICE_LOCK(clk);
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/* Setting to slow mode during frequency change */
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reg = (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) <<
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RK_CLK_PLL_MASK_SHIFT;
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dprintf("Set PLL_MODEREG to %x\n", reg);
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WRITE4(clk, sc->mode_reg, reg);
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/* Reset PLL */
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WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET |
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RK3066_CLK_PLL_RESET << RK_CLK_PLL_MASK_SHIFT);
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/* Setting postdiv and refdiv */
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reg = 0;
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reg |= RK3066_CLK_PLL_POSTDIV_MASK << 16;
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reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT;
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reg |= RK3066_CLK_PLL_REFDIV_MASK << 16;
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reg |= (rates->refdiv - 1)<< RK3066_CLK_PLL_REFDIV_SHIFT;
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dprintf("Set PLL_CON0 to %x\n", reg);
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WRITE4(clk, sc->base_offset, reg);
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/* Setting fbdiv (no write mask)*/
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READ4(clk, sc->base_offset + 4, ®);
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reg &= ~RK3066_CLK_PLL_FBDIV_MASK;
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reg |= RK3066_CLK_PLL_FBDIV_MASK << 16;
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reg = (rates->fbdiv - 1) << RK3066_CLK_PLL_FBDIV_SHIFT;
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dprintf("Set PLL_CON1 to %x\n", reg);
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WRITE4(clk, sc->base_offset + 0x4, reg);
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/* PLL loop bandwidth adjust */
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reg = rates->bwadj - 1;
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dprintf("Set PLL_CON2 to %x (%x)\n", reg, rates->bwadj);
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WRITE4(clk, sc->base_offset + 0x8, reg);
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/* Clear reset */
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WRITE4(clk, sc->base_offset + 12,
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RK3066_CLK_PLL_RESET << RK_CLK_PLL_MASK_SHIFT);
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DELAY(100000);
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/* Reading lock */
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for (timeout = 1000; timeout >= 0; timeout--) {
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READ4(clk, sc->base_offset + 0x4, ®);
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if ((reg & RK3066_CLK_PLL_LOCK_MASK) != 0)
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break;
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DELAY(1);
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}
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rv = 0;
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if (timeout < 0) {
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device_printf(clknode_get_device(clk),
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"%s - Timedout while waiting for lock.\n",
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clknode_get_name(clk));
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dprintf("PLL_CON1: %x\n", reg);
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rv = ETIMEDOUT;
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}
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/* Set back to normal mode */
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reg = (RK3066_CLK_PLL_MODE_NORMAL << sc->mode_shift);
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reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) <<
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RK_CLK_PLL_MASK_SHIFT;
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dprintf("Set PLL_MODEREG to %x\n", reg);
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WRITE4(clk, sc->mode_reg, reg);
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DEVICE_UNLOCK(clk);
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*stop = 1;
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rv = clknode_set_parent_by_idx(clk, 1);
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return (rv);
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}
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static clknode_method_t rk3066_clk_pll_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, rk3066_clk_pll_init),
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CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate),
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CLKNODEMETHOD(clknode_recalc_freq, rk3066_clk_pll_recalc),
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CLKNODEMETHOD(clknode_set_freq, rk3066_clk_pll_set_freq),
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CLKNODEMETHOD(clknode_set_mux, rk3066_clk_pll_set_mux),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(rk3066_clk_pll_clknode, rk3066_clk_pll_clknode_class,
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rk3066_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class);
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int
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rk3066_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef)
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{
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struct clknode *clk;
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struct rk_clk_pll_sc *sc;
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clk = clknode_create(clkdom, &rk3066_clk_pll_clknode_class,
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&clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->base_offset = clkdef->base_offset;
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sc->gate_offset = clkdef->gate_offset;
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sc->gate_shift = clkdef->gate_shift;
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sc->mode_reg = clkdef->mode_reg;
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sc->mode_shift = clkdef->mode_shift;
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sc->flags = clkdef->flags;
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sc->rates = clkdef->rates;
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sc->frac_rates = clkdef->frac_rates;
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clknode_register(clkdom, clk);
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return (0);
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}
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#define RK3328_CLK_PLL_FBDIV_OFFSET 0
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#define RK3328_CLK_PLL_FBDIV_SHIFT 0
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#define RK3328_CLK_PLL_FBDIV_MASK 0xFFF
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#define RK3328_CLK_PLL_POSTDIV1_OFFSET 0
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#define RK3328_CLK_PLL_POSTDIV1_SHIFT 12
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#define RK3328_CLK_PLL_POSTDIV1_MASK 0x7000
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#define RK3328_CLK_PLL_DSMPD_OFFSET 4
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#define RK3328_CLK_PLL_DSMPD_SHIFT 12
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#define RK3328_CLK_PLL_DSMPD_MASK 0x1000
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#define RK3328_CLK_PLL_REFDIV_OFFSET 4
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#define RK3328_CLK_PLL_REFDIV_SHIFT 0
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#define RK3328_CLK_PLL_REFDIV_MASK 0x3F
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#define RK3328_CLK_PLL_POSTDIV2_OFFSET 4
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#define RK3328_CLK_PLL_POSTDIV2_SHIFT 6
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#define RK3328_CLK_PLL_POSTDIV2_MASK 0x1C0
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#define RK3328_CLK_PLL_FRAC_OFFSET 8
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#define RK3328_CLK_PLL_FRAC_SHIFT 0
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#define RK3328_CLK_PLL_FRAC_MASK 0xFFFFFF
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#define RK3328_CLK_PLL_LOCK_MASK 0x400
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#define RK3328_CLK_PLL_MODE_SLOW 0
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#define RK3328_CLK_PLL_MODE_NORMAL 1
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#define RK3328_CLK_PLL_MODE_MASK 0x1
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static int
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rk3328_clk_pll_init(struct clknode *clk, device_t dev)
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{
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struct rk_clk_pll_sc *sc;
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sc = clknode_get_softc(clk);
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static int
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rk3328_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct rk_clk_pll_sc *sc;
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uint64_t rate;
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uint32_t dsmpd, refdiv, fbdiv;
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uint32_t postdiv1, postdiv2, frac;
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uint32_t raw1, raw2, raw3;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->base_offset, &raw1);
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READ4(clk, sc->base_offset + 4, &raw2);
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READ4(clk, sc->base_offset + 8, &raw3);
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fbdiv = (raw1 & RK3328_CLK_PLL_FBDIV_MASK) >> RK3328_CLK_PLL_FBDIV_SHIFT;
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postdiv1 = (raw1 & RK3328_CLK_PLL_POSTDIV1_MASK) >> RK3328_CLK_PLL_POSTDIV1_SHIFT;
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dsmpd = (raw2 & RK3328_CLK_PLL_DSMPD_MASK) >> RK3328_CLK_PLL_DSMPD_SHIFT;
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refdiv = (raw2 & RK3328_CLK_PLL_REFDIV_MASK) >> RK3328_CLK_PLL_REFDIV_SHIFT;
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postdiv2 = (raw2 & RK3328_CLK_PLL_POSTDIV2_MASK) >> RK3328_CLK_PLL_POSTDIV2_SHIFT;
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frac = (raw3 & RK3328_CLK_PLL_FRAC_MASK) >> RK3328_CLK_PLL_FRAC_SHIFT;
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DEVICE_UNLOCK(clk);
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rate = *freq * fbdiv / refdiv;
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if (dsmpd == 0) {
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/* Fractional mode */
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uint64_t frac_rate;
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frac_rate = *freq * frac / refdiv;
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rate += frac_rate >> 24;
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}
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*freq = rate / postdiv1 / postdiv2;
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if (*freq % 2)
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*freq = *freq + 1;
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return (0);
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}
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static int
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rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
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int flags, int *stop)
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{
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struct rk_clk_pll_rate *rates;
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struct rk_clk_pll_sc *sc;
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uint32_t reg;
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int timeout;
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sc = clknode_get_softc(clk);
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if (sc->rates)
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rates = sc->rates;
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else if (sc->frac_rates)
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rates = sc->frac_rates;
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else
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return (EINVAL);
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for (; rates->freq; rates++) {
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if (rates->freq == *fout)
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break;
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}
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if (rates->freq == 0) {
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*stop = 1;
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return (EINVAL);
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}
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DEVICE_LOCK(clk);
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/* Setting to slow mode during frequency change */
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reg = (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) <<
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RK_CLK_PLL_MASK_SHIFT;
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dprintf("Set PLL_MODEREG to %x\n", reg);
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WRITE4(clk, sc->mode_reg, reg);
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/* Setting postdiv1 and fbdiv */
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reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) |
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(rates->fbdiv << RK3328_CLK_PLL_FBDIV_SHIFT);
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reg |= (RK3328_CLK_PLL_POSTDIV1_MASK | RK3328_CLK_PLL_FBDIV_MASK) << 16;
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dprintf("Set PLL_CON0 to %x\n", reg);
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WRITE4(clk, sc->base_offset, reg);
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/* Setting dsmpd, postdiv2 and refdiv */
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reg = (rates->dsmpd << RK3328_CLK_PLL_DSMPD_SHIFT) |
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(rates->postdiv2 << RK3328_CLK_PLL_POSTDIV2_SHIFT) |
|
|
(rates->refdiv << RK3328_CLK_PLL_REFDIV_SHIFT);
|
|
reg |= (RK3328_CLK_PLL_DSMPD_MASK |
|
|
RK3328_CLK_PLL_POSTDIV2_MASK |
|
|
RK3328_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT;
|
|
dprintf("Set PLL_CON1 to %x\n", reg);
|
|
WRITE4(clk, sc->base_offset + 0x4, reg);
|
|
|
|
/* Setting frac */
|
|
READ4(clk, sc->base_offset + 0x8, ®);
|
|
reg &= ~RK3328_CLK_PLL_FRAC_MASK;
|
|
reg |= rates->frac << RK3328_CLK_PLL_FRAC_SHIFT;
|
|
dprintf("Set PLL_CON2 to %x\n", reg);
|
|
WRITE4(clk, sc->base_offset + 0x8, reg);
|
|
|
|
/* Reading lock */
|
|
for (timeout = 1000; timeout; timeout--) {
|
|
READ4(clk, sc->base_offset + 0x4, ®);
|
|
if ((reg & RK3328_CLK_PLL_LOCK_MASK) == 0)
|
|
break;
|
|
DELAY(1);
|
|
}
|
|
|
|
/* Set back to normal mode */
|
|
reg = (RK3328_CLK_PLL_MODE_NORMAL << sc->mode_shift);
|
|
reg |= (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) <<
|
|
RK_CLK_PLL_MASK_SHIFT;
|
|
dprintf("Set PLL_MODEREG to %x\n", reg);
|
|
WRITE4(clk, sc->mode_reg, reg);
|
|
|
|
DEVICE_UNLOCK(clk);
|
|
|
|
*stop = 1;
|
|
return (0);
|
|
}
|
|
|
|
static clknode_method_t rk3328_clk_pll_clknode_methods[] = {
|
|
/* Device interface */
|
|
CLKNODEMETHOD(clknode_init, rk3328_clk_pll_init),
|
|
CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate),
|
|
CLKNODEMETHOD(clknode_recalc_freq, rk3328_clk_pll_recalc),
|
|
CLKNODEMETHOD(clknode_set_freq, rk3328_clk_pll_set_freq),
|
|
CLKNODEMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_1(rk3328_clk_pll_clknode, rk3328_clk_pll_clknode_class,
|
|
rk3328_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class);
|
|
|
|
int
|
|
rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef)
|
|
{
|
|
struct clknode *clk;
|
|
struct rk_clk_pll_sc *sc;
|
|
|
|
clk = clknode_create(clkdom, &rk3328_clk_pll_clknode_class,
|
|
&clkdef->clkdef);
|
|
if (clk == NULL)
|
|
return (1);
|
|
|
|
sc = clknode_get_softc(clk);
|
|
|
|
sc->base_offset = clkdef->base_offset;
|
|
sc->gate_offset = clkdef->gate_offset;
|
|
sc->gate_shift = clkdef->gate_shift;
|
|
sc->mode_reg = clkdef->mode_reg;
|
|
sc->mode_shift = clkdef->mode_shift;
|
|
sc->flags = clkdef->flags;
|
|
sc->rates = clkdef->rates;
|
|
sc->frac_rates = clkdef->frac_rates;
|
|
|
|
clknode_register(clkdom, clk);
|
|
|
|
return (0);
|
|
}
|
|
|
|
#define RK3399_CLK_PLL_FBDIV_OFFSET 0
|
|
#define RK3399_CLK_PLL_FBDIV_SHIFT 0
|
|
#define RK3399_CLK_PLL_FBDIV_MASK 0xFFF
|
|
|
|
#define RK3399_CLK_PLL_POSTDIV2_OFFSET 4
|
|
#define RK3399_CLK_PLL_POSTDIV2_SHIFT 12
|
|
#define RK3399_CLK_PLL_POSTDIV2_MASK 0x7000
|
|
|
|
#define RK3399_CLK_PLL_POSTDIV1_OFFSET 4
|
|
#define RK3399_CLK_PLL_POSTDIV1_SHIFT 8
|
|
#define RK3399_CLK_PLL_POSTDIV1_MASK 0x700
|
|
|
|
#define RK3399_CLK_PLL_REFDIV_OFFSET 4
|
|
#define RK3399_CLK_PLL_REFDIV_SHIFT 0
|
|
#define RK3399_CLK_PLL_REFDIV_MASK 0x3F
|
|
|
|
#define RK3399_CLK_PLL_FRAC_OFFSET 8
|
|
#define RK3399_CLK_PLL_FRAC_SHIFT 0
|
|
#define RK3399_CLK_PLL_FRAC_MASK 0xFFFFFF
|
|
|
|
#define RK3399_CLK_PLL_DSMPD_OFFSET 0xC
|
|
#define RK3399_CLK_PLL_DSMPD_SHIFT 3
|
|
#define RK3399_CLK_PLL_DSMPD_MASK 0x8
|
|
|
|
#define RK3399_CLK_PLL_LOCK_OFFSET 8
|
|
#define RK3399_CLK_PLL_LOCK_MASK 0x400
|
|
|
|
#define RK3399_CLK_PLL_MODE_OFFSET 0xC
|
|
#define RK3399_CLK_PLL_MODE_MASK 0x300
|
|
#define RK3399_CLK_PLL_MODE_SLOW 0
|
|
#define RK3399_CLK_PLL_MODE_NORMAL 1
|
|
#define RK3399_CLK_PLL_MODE_DEEPSLOW 2
|
|
#define RK3399_CLK_PLL_MODE_SHIFT 8
|
|
|
|
#define RK3399_CLK_PLL_WRITE_MASK 0xFFFF0000
|
|
|
|
static int
|
|
rk3399_clk_pll_init(struct clknode *clk, device_t dev)
|
|
{
|
|
struct rk_clk_pll_sc *sc;
|
|
|
|
sc = clknode_get_softc(clk);
|
|
clknode_init_parent_idx(clk, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
|
|
{
|
|
struct rk_clk_pll_sc *sc;
|
|
uint32_t dsmpd, refdiv, fbdiv;
|
|
uint32_t postdiv1, postdiv2, fracdiv;
|
|
uint32_t con1, con2, con3, con4;
|
|
uint64_t foutvco;
|
|
uint32_t mode;
|
|
sc = clknode_get_softc(clk);
|
|
|
|
DEVICE_LOCK(clk);
|
|
READ4(clk, sc->base_offset, &con1);
|
|
READ4(clk, sc->base_offset + 4, &con2);
|
|
READ4(clk, sc->base_offset + 8, &con3);
|
|
READ4(clk, sc->base_offset + 0xC, &con4);
|
|
DEVICE_UNLOCK(clk);
|
|
|
|
/*
|
|
* if we are in slow mode the output freq
|
|
* is the parent one, the 24Mhz external oscillator
|
|
* if we are in deep mode the output freq is 32.768khz
|
|
*/
|
|
mode = (con4 & RK3399_CLK_PLL_MODE_MASK) >> RK3399_CLK_PLL_MODE_SHIFT;
|
|
if (mode == RK3399_CLK_PLL_MODE_SLOW) {
|
|
dprintf("pll in slow mode, con4=%x\n", con4);
|
|
return (0);
|
|
} else if (mode == RK3399_CLK_PLL_MODE_DEEPSLOW) {
|
|
dprintf("pll in deep slow, con4=%x\n", con4);
|
|
*freq = 32768;
|
|
return (0);
|
|
}
|
|
|
|
dprintf("con0: %x\n", con1);
|
|
dprintf("con1: %x\n", con2);
|
|
dprintf("con2: %x\n", con3);
|
|
dprintf("con3: %x\n", con4);
|
|
|
|
fbdiv = (con1 & RK3399_CLK_PLL_FBDIV_MASK)
|
|
>> RK3399_CLK_PLL_FBDIV_SHIFT;
|
|
|
|
postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK)
|
|
>> RK3399_CLK_PLL_POSTDIV1_SHIFT;
|
|
postdiv2 = (con2 & RK3399_CLK_PLL_POSTDIV2_MASK)
|
|
>> RK3399_CLK_PLL_POSTDIV2_SHIFT;
|
|
refdiv = (con2 & RK3399_CLK_PLL_REFDIV_MASK)
|
|
>> RK3399_CLK_PLL_REFDIV_SHIFT;
|
|
|
|
fracdiv = (con3 & RK3399_CLK_PLL_FRAC_MASK)
|
|
>> RK3399_CLK_PLL_FRAC_SHIFT;
|
|
fracdiv >>= 24;
|
|
|
|
dsmpd = (con4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT;
|
|
|
|
dprintf("fbdiv: %d\n", fbdiv);
|
|
dprintf("postdiv1: %d\n", postdiv1);
|
|
dprintf("postdiv2: %d\n", postdiv2);
|
|
dprintf("refdiv: %d\n", refdiv);
|
|
dprintf("fracdiv: %d\n", fracdiv);
|
|
dprintf("dsmpd: %d\n", dsmpd);
|
|
|
|
dprintf("parent freq=%ju\n", *freq);
|
|
|
|
if (dsmpd == 0) {
|
|
/* Fractional mode */
|
|
foutvco = *freq / refdiv * (fbdiv + fracdiv);
|
|
} else {
|
|
/* Integer mode */
|
|
foutvco = *freq / refdiv * fbdiv;
|
|
}
|
|
dprintf("foutvco: %ju\n", foutvco);
|
|
|
|
*freq = foutvco / postdiv1 / postdiv2;
|
|
dprintf("freq: %ju\n", *freq);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
|
|
int flags, int *stop)
|
|
{
|
|
struct rk_clk_pll_rate *rates;
|
|
struct rk_clk_pll_sc *sc;
|
|
uint32_t reg;
|
|
int timeout;
|
|
|
|
sc = clknode_get_softc(clk);
|
|
|
|
if (sc->rates)
|
|
rates = sc->rates;
|
|
else if (sc->frac_rates)
|
|
rates = sc->frac_rates;
|
|
else
|
|
return (EINVAL);
|
|
|
|
for (; rates->freq; rates++) {
|
|
if (rates->freq == *fout)
|
|
break;
|
|
}
|
|
if (rates->freq == 0) {
|
|
*stop = 1;
|
|
return (EINVAL);
|
|
}
|
|
|
|
DEVICE_LOCK(clk);
|
|
|
|
/* Set to slow mode during frequency change */
|
|
reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT;
|
|
reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
|
|
WRITE4(clk, sc->base_offset + 0xC, reg);
|
|
|
|
/* Setting fbdiv */
|
|
reg = rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT;
|
|
reg |= RK3399_CLK_PLL_FBDIV_MASK << RK_CLK_PLL_MASK_SHIFT;
|
|
WRITE4(clk, sc->base_offset, reg);
|
|
|
|
/* Setting postdiv1, postdiv2 and refdiv */
|
|
reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT;
|
|
reg |= rates->postdiv2 << RK3399_CLK_PLL_POSTDIV2_SHIFT;
|
|
reg |= rates->refdiv << RK3399_CLK_PLL_REFDIV_SHIFT;
|
|
reg |= (RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK |
|
|
RK3399_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT;
|
|
WRITE4(clk, sc->base_offset + 0x4, reg);
|
|
|
|
/* Setting frac */
|
|
READ4(clk, sc->base_offset + 0x8, ®);
|
|
reg &= ~RK3399_CLK_PLL_FRAC_MASK;
|
|
reg |= rates->frac << RK3399_CLK_PLL_FRAC_SHIFT;
|
|
WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK);
|
|
|
|
/* Set dsmpd */
|
|
reg = rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT;
|
|
reg |= RK3399_CLK_PLL_DSMPD_MASK << RK_CLK_PLL_MASK_SHIFT;
|
|
WRITE4(clk, sc->base_offset + 0xC, reg);
|
|
|
|
/* Reading lock */
|
|
for (timeout = 1000; timeout; timeout--) {
|
|
READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, ®);
|
|
if ((reg & RK3399_CLK_PLL_LOCK_MASK) == 0)
|
|
break;
|
|
DELAY(1);
|
|
}
|
|
|
|
/* Set back to normal mode */
|
|
reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
|
|
reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
|
|
WRITE4(clk, sc->base_offset + 0xC, reg);
|
|
|
|
DEVICE_UNLOCK(clk);
|
|
|
|
*stop = 1;
|
|
return (0);
|
|
}
|
|
|
|
static clknode_method_t rk3399_clk_pll_clknode_methods[] = {
|
|
/* Device interface */
|
|
CLKNODEMETHOD(clknode_init, rk3399_clk_pll_init),
|
|
CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate),
|
|
CLKNODEMETHOD(clknode_recalc_freq, rk3399_clk_pll_recalc),
|
|
CLKNODEMETHOD(clknode_set_freq, rk3399_clk_pll_set_freq),
|
|
CLKNODEMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_1(rk3399_clk_pll_clknode, rk3399_clk_pll_clknode_class,
|
|
rk3399_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class);
|
|
|
|
int
|
|
rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef)
|
|
{
|
|
struct clknode *clk;
|
|
struct rk_clk_pll_sc *sc;
|
|
|
|
clk = clknode_create(clkdom, &rk3399_clk_pll_clknode_class,
|
|
&clkdef->clkdef);
|
|
if (clk == NULL)
|
|
return (1);
|
|
|
|
sc = clknode_get_softc(clk);
|
|
|
|
sc->base_offset = clkdef->base_offset;
|
|
sc->gate_offset = clkdef->gate_offset;
|
|
sc->gate_shift = clkdef->gate_shift;
|
|
sc->flags = clkdef->flags;
|
|
sc->rates = clkdef->rates;
|
|
sc->frac_rates = clkdef->frac_rates;
|
|
|
|
clknode_register(clkdom, clk);
|
|
|
|
return (0);
|
|
}
|