mirror of https://github.com/F-Stack/f-stack.git
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef __CN10K_IPSEC_LA_OPS_H__
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#define __CN10K_IPSEC_LA_OPS_H__
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#include <rte_crypto_sym.h>
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#include <rte_security.h>
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#include "cn10k_cryptodev.h"
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#include "cn10k_ipsec.h"
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#include "cnxk_cryptodev.h"
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static inline void
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ipsec_po_sa_iv_set(struct cn10k_sec_session *sess, struct rte_crypto_op *cop)
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{
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uint64_t *iv = &sess->sa.out_sa.iv.u64[0];
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uint64_t *tmp_iv;
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memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), 16);
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tmp_iv = (uint64_t *)iv;
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*tmp_iv = rte_be_to_cpu_64(*tmp_iv);
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tmp_iv = (uint64_t *)(iv + 1);
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*tmp_iv = rte_be_to_cpu_64(*tmp_iv);
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}
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static inline void
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ipsec_po_sa_aes_gcm_iv_set(struct cn10k_sec_session *sess, struct rte_crypto_op *cop)
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{
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uint8_t *iv = &sess->sa.out_sa.iv.s.iv_dbg1[0];
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uint32_t *tmp_iv;
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memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), 4);
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tmp_iv = (uint32_t *)iv;
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*tmp_iv = rte_be_to_cpu_32(*tmp_iv);
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iv = &sess->sa.out_sa.iv.s.iv_dbg2[0];
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memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset + 4), 4);
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tmp_iv = (uint32_t *)iv;
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*tmp_iv = rte_be_to_cpu_32(*tmp_iv);
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}
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static __rte_always_inline int
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process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
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struct cpt_inst_s *inst)
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{
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struct rte_crypto_sym_op *sym_op = cop->sym;
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struct rte_mbuf *m_src = sym_op->m_src;
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uint64_t inst_w4_u64 = sess->inst.w4;
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uint64_t dptr;
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if (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) {
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plt_dp_err("Not enough tail room");
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return -ENOMEM;
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}
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RTE_SET_USED(lf);
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#ifdef LA_IPSEC_DEBUG
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if (sess->sa.out_sa.w2.s.iv_src == ROC_IE_OT_SA_IV_SRC_FROM_SA) {
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if (sess->sa.out_sa.w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM ||
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sess->sa.out_sa.w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CCM ||
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sess->sa.out_sa.w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC)
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ipsec_po_sa_aes_gcm_iv_set(sess, cop);
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else
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ipsec_po_sa_iv_set(sess, cop);
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}
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/* Trigger CTX reload to fetch new data from DRAM */
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roc_cpt_lf_ctx_reload(lf, &sess->sa.out_sa);
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rte_delay_ms(1);
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#endif
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if (m_src->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)
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inst_w4_u64 &= ~BIT_ULL(33);
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if (m_src->ol_flags & RTE_MBUF_F_TX_L4_MASK)
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inst_w4_u64 &= ~BIT_ULL(32);
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/* Prepare CPT instruction */
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inst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src);
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dptr = rte_pktmbuf_mtod(m_src, uint64_t);
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inst->dptr = dptr;
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return 0;
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}
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static __rte_always_inline int
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process_inb_sa(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, struct cpt_inst_s *inst)
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{
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struct rte_crypto_sym_op *sym_op = cop->sym;
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struct rte_mbuf *m_src = sym_op->m_src;
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uint64_t dptr;
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/* Prepare CPT instruction */
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inst->w4.u64 = sess->inst.w4 | rte_pktmbuf_pkt_len(m_src);
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dptr = rte_pktmbuf_mtod(m_src, uint64_t);
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inst->dptr = dptr;
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return 0;
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}
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#endif /* __CN10K_IPSEC_LA_OPS_H__ */
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