mirror of https://github.com/F-Stack/f-stack.git
98 lines
4.1 KiB
INI
98 lines
4.1 KiB
INI
; BSD LICENSE
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;
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; Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; An edge router typically sits between two networks such as the provider
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; core network and the provider access network. A typical packet processing
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; pipeline for the downstream traffic (i.e. traffic from core to access
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; network) contains the following functional blocks: Packet RX & Routing,
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; Traffic management and Packet TX. The input packets are assumed to be
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; IPv4, while the output packets are Q-in-Q IPv4.
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;
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; A simple implementation for this functional pipeline is presented below.
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;
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; Packet Rx & Traffic Management Packet Tx
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; Routing (Pass-Through) (Pass-Through)
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; _____________________ SWQ0 ______________________ SWQ4 _____________________
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; RXQ0.0 --->| |----->| |----->| |---> TXQ0.0
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; | | SWQ1 | | SWQ5 | |
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; RXQ1.0 --->| |----->| |----->| |---> TXQ1.0
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; | (P1) | SWQ2 | (P2) | SWQ6 | (P3) |
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; RXQ2.0 --->| |----->| |----->| |---> TXQ2.0
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; | | SWQ3 | | SWQ7 | |
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; RXQ3.0 --->| |----->| |----->| |---> TXQ3.0
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; |_____________________| |______________________| |_____________________|
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; | | ^ | ^ | ^ | ^
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; | |__| |__| |__| |__|
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; +--> SINK0 TM0 TM1 TM2 TM3
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; (Default)
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;
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; Input packet: Ethernet/IPv4
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; Output packet: Ethernet/QinQ/IPv4
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;
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; Packet buffer layout:
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; # Field Name Offset (Bytes) Size (Bytes)
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; 0 Mbuf 0 128
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; 1 Headroom 128 128
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; 2 Ethernet header 256 14
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; 3 IPv4 header 270 20
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[EAL]
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log_level = 0
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[PIPELINE0]
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type = MASTER
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core = 0
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[PIPELINE1]
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type = ROUTING
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core = 1
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pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
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pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
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encap = ethernet_qinq
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qinq_sched = test
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ip_hdr_offset = 270
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[PIPELINE2]
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type = PASS-THROUGH
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core = 2
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pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 TM0 TM1 TM2 TM3
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pktq_out = TM0 TM1 TM2 TM3 SWQ4 SWQ5 SWQ6 SWQ7
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[PIPELINE3]
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type = PASS-THROUGH
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core = 3
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pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
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pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0
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[MEMPOOL0]
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pool_size = 2M
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