mirror of https://github.com/F-Stack/f-stack.git
171 lines
3.6 KiB
C
171 lines
3.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2022 Marvell.
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*/
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#ifndef __ML_HW_H__
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#define __ML_HW_H__
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#include <stdint.h>
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/* Constants */
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#define ML_ANBX_NR 0x3
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/* Base offsets */
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#define ML_MLAB_BLK_OFFSET 0x20000000 /* CNF10KB */
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#define ML_AXI_START_ADDR 0x800000000
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/* MLW register offsets / ML_PF_BAR0 */
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#define ML_CFG 0x10000
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#define ML_MLR_BASE 0x10008
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#define ML_AXI_BRIDGE_CTRL(a) (0x10020 | (uint64_t)(a) << 3)
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#define ML_JOB_MGR_CTRL 0x10060
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#define ML_CORE_INT_LO 0x10140
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#define ML_CORE_INT_HI 0x10160
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#define ML_JCMDQ_IN(a) (0x11000 | (uint64_t)(a) << 3) /* CN10KA */
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#define ML_JCMDQ_STATUS 0x11010 /* CN10KA */
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#define ML_STGX_STATUS(a) (0x11020 | (uint64_t)(a) << 3) /* CNF10KB */
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#define ML_STG_CONTROL 0x11100 /* CNF10KB */
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#define ML_PNB_CMD_TYPE 0x113a0 /* CNF10KB */
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#define ML_SCRATCH(a) (0x14000 | (uint64_t)(a) << 3)
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#define ML_ANBX_BACKP_DISABLE(a) (0x18000 | (uint64_t)(a) << 12) /* CN10KA */
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#define ML_ANBX_NCBI_P_OVR(a) (0x18010 | (uint64_t)(a) << 12) /* CN10KA */
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#define ML_ANBX_NCBI_NP_OVR(a) (0x18020 | (uint64_t)(a) << 12) /* CN10KA */
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/* MLIP configuration register offsets / ML_PF_BAR0 */
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#define ML_SW_RST_CTRL 0x12084000
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#define ML_A35_0_RST_VECTOR_BASE_W(a) (0x12084014 + (a) * (0x04))
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#define ML_A35_1_RST_VECTOR_BASE_W(a) (0x1208401c + (a) * (0x04))
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/* MLW scratch register offsets */
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#define ML_SCRATCH_WORK_PTR (ML_SCRATCH(0))
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#define ML_SCRATCH_FW_CTRL (ML_SCRATCH(1))
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#define ML_SCRATCH_DBG_BUFFER_HEAD_C0 (ML_SCRATCH(2))
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#define ML_SCRATCH_DBG_BUFFER_TAIL_C0 (ML_SCRATCH(3))
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#define ML_SCRATCH_DBG_BUFFER_HEAD_C1 (ML_SCRATCH(4))
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#define ML_SCRATCH_DBG_BUFFER_TAIL_C1 (ML_SCRATCH(5))
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#define ML_SCRATCH_EXCEPTION_SP_C0 (ML_SCRATCH(6))
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#define ML_SCRATCH_EXCEPTION_SP_C1 (ML_SCRATCH(7))
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/* ML job completion structure */
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struct ml_jce_s {
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/* WORD 0 */
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union ml_jce_w0 {
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struct {
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uint64_t rsvd_0_3 : 4;
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/* Reserved for future architecture */
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uint64_t ggrp_h : 2;
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/* Tag type */
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uint64_t ttype : 2;
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/* Physical function number */
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uint64_t pf_func : 16;
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/* Unused [7] + Guest Group [6:0] */
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uint64_t ggrp : 8;
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/* Tag */
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uint64_t tag : 32;
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} s;
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uint64_t u64;
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} w0;
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/* WORD 1 */
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union ml_jce_w1 {
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struct {
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/* Work queue pointer */
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uint64_t wqp : 53;
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uint64_t rsvd_53_63 : 11;
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} s;
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uint64_t u64;
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} w1;
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};
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/* ML job command structure */
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struct ml_job_cmd_s {
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/* WORD 0 */
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union ml_job_cmd_w0 {
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struct {
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uint64_t rsvd_0_63;
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} s;
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uint64_t u64;
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} w0;
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/* WORD 1 */
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union ml_job_cmd_w1 {
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struct {
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/* Job pointer */
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uint64_t jobptr : 53;
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uint64_t rsvd_53_63 : 11;
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} s;
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uint64_t u64;
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} w1;
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};
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/* ML A35 0 RST vector base structure */
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union ml_a35_0_rst_vector_base_s {
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struct {
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/* Base address */
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uint64_t addr : 37;
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uint64_t rsvd_37_63 : 27;
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} s;
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struct {
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/* WORD 0 */
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uint32_t w0;
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/* WORD 1 */
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uint32_t w1;
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} w;
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uint64_t u64;
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};
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/* ML A35 1 RST vector base structure */
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union ml_a35_1_rst_vector_base_s {
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struct {
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/* Base address */
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uint64_t addr : 37;
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uint64_t rsvd_37_63 : 27;
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} s;
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struct {
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/* WORD 0 */
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uint32_t w0;
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/* WORD 1 */
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uint32_t w1;
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} w;
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uint64_t u64;
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};
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/* Work pointer scratch register */
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union ml_scratch_work_ptr_s {
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struct {
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/* Work pointer */
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uint64_t work_ptr : 37;
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uint64_t rsvd_37_63 : 27;
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} s;
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uint64_t u64;
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};
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/* Firmware control scratch register */
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union ml_scratch_fw_ctrl_s {
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struct {
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uint64_t rsvd_0_15 : 16;
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/* Valid job bit */
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uint64_t valid : 1;
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/* Done status bit */
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uint64_t done : 1;
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uint64_t rsvd_18_63 : 46;
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} s;
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uint64_t u64;
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};
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#endif /* __ML_HW_H__ */
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