mirror of https://github.com/F-Stack/f-stack.git
844 lines
18 KiB
ArmAsm
844 lines
18 KiB
ArmAsm
/*-
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* Copyright (c) 2012-2014 Andrew Turner
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.inc"
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#include "opt_kstack_pages.h"
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#include <sys/syscall.h>
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#include <machine/asm.h>
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#include <machine/armreg.h>
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#include <machine/hypervisor.h>
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#include <machine/param.h>
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#include <machine/pte.h>
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#include <machine/vm.h>
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#include <machine/vmparam.h>
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#define VIRT_BITS 48
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#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
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.globl kernbase
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.set kernbase, KERNBASE
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/*
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* We assume:
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* MMU on with an identity map, or off
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* D-Cache: off
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* I-Cache: on or off
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* We are loaded at a 2MiB aligned address
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*/
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ENTRY(_start)
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/* Drop to EL1 */
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bl drop_to_el1
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/*
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* Disable the MMU. We may have entered the kernel with it on and
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* will need to update the tables later. If this has been set up
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* with anything other than a VA == PA map then this will fail,
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* but in this case the code to find where we are running from
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* would have also failed.
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*/
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dsb sy
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mrs x2, sctlr_el1
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bic x2, x2, SCTLR_M
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msr sctlr_el1, x2
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isb
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/* Set the context id */
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msr contextidr_el1, xzr
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/* Get the virt -> phys offset */
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bl get_virt_delta
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/*
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* At this point:
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* x29 = PA - VA
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* x28 = Our physical load address
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*/
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/* Create the page tables */
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bl create_pagetables
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/*
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* At this point:
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* x27 = TTBR0 table
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* x26 = Kernel L1 table
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* x24 = TTBR1 table
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*/
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/* Enable the mmu */
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bl start_mmu
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/* Load the new ttbr0 pagetable */
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adrp x27, pagetable_l0_ttbr0
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add x27, x27, :lo12:pagetable_l0_ttbr0
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/* Jump to the virtual address space */
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ldr x15, .Lvirtdone
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br x15
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virtdone:
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/* Set up the stack */
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adrp x25, initstack_end
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add x25, x25, :lo12:initstack_end
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mov sp, x25
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sub sp, sp, #PCB_SIZE
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/* Zero the BSS */
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ldr x15, .Lbss
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ldr x14, .Lend
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1:
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str xzr, [x15], #8
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cmp x15, x14
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b.lo 1b
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/* Backup the module pointer */
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mov x1, x0
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/* Make the page table base a virtual address */
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sub x26, x26, x29
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sub x24, x24, x29
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sub sp, sp, #BOOTPARAMS_SIZE
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mov x0, sp
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/* Degate the delda so it is VA -> PA */
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neg x29, x29
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str x1, [x0, #BP_MODULEP]
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str x26, [x0, #BP_KERN_L1PT]
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str x29, [x0, #BP_KERN_DELTA]
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adrp x25, initstack
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add x25, x25, :lo12:initstack
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str x25, [x0, #BP_KERN_STACK]
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str x24, [x0, #BP_KERN_L0PT]
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str x27, [x0, #BP_KERN_TTBR0]
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str x23, [x0, #BP_BOOT_EL]
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/* trace back starts here */
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mov fp, #0
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/* Branch to C code */
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bl initarm
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/* We are done with the boot params */
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add sp, sp, #BOOTPARAMS_SIZE
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bl mi_startup
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/* We should not get here */
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brk 0
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.align 3
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.Lvirtdone:
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.quad virtdone
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.Lbss:
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.quad __bss_start
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.Lend:
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.quad __bss_end
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END(_start)
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#ifdef SMP
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/*
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* mpentry(unsigned long)
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*
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* Called by a core when it is being brought online.
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* The data in x0 is passed straight to init_secondary.
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*/
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ENTRY(mpentry)
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/* Disable interrupts */
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msr daifset, #2
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/* Drop to EL1 */
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bl drop_to_el1
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/* Set the context id */
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msr contextidr_el1, xzr
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/* Load the kernel page table */
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adrp x24, pagetable_l0_ttbr1
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add x24, x24, :lo12:pagetable_l0_ttbr1
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/* Load the identity page table */
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adrp x27, pagetable_l0_ttbr0_boostrap
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add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap
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/* Enable the mmu */
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bl start_mmu
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/* Load the new ttbr0 pagetable */
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adrp x27, pagetable_l0_ttbr0
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add x27, x27, :lo12:pagetable_l0_ttbr0
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/* Jump to the virtual address space */
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ldr x15, =mp_virtdone
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br x15
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mp_virtdone:
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/* Start using the AP boot stack */
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ldr x4, =bootstack
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ldr x4, [x4]
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mov sp, x4
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/* Load the kernel ttbr0 pagetable */
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msr ttbr0_el1, x27
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isb
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/* Invalidate the TLB */
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tlbi vmalle1
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dsb sy
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isb
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b init_secondary
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END(mpentry)
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#endif
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/*
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* If we are started in EL2, configure the required hypervisor
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* registers and drop to EL1.
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*/
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LENTRY(drop_to_el1)
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mrs x23, CurrentEL
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lsr x23, x23, #2
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cmp x23, #0x2
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b.eq 1f
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ret
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1:
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/* Configure the Hypervisor */
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mov x2, #(HCR_RW)
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msr hcr_el2, x2
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/* Load the Virtualization Process ID Register */
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mrs x2, midr_el1
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msr vpidr_el2, x2
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/* Load the Virtualization Multiprocess ID Register */
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mrs x2, mpidr_el1
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msr vmpidr_el2, x2
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/* Set the bits that need to be 1 in sctlr_el1 */
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ldr x2, .Lsctlr_res1
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msr sctlr_el1, x2
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/* Don't trap to EL2 for exceptions */
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mov x2, #CPTR_RES1
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msr cptr_el2, x2
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/* Don't trap to EL2 for CP15 traps */
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msr hstr_el2, xzr
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/* Enable access to the physical timers at EL1 */
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mrs x2, cnthctl_el2
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orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
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msr cnthctl_el2, x2
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/* Set the counter offset to a known value */
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msr cntvoff_el2, xzr
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/* Hypervisor trap functions */
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adrp x2, hyp_vectors
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add x2, x2, :lo12:hyp_vectors
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msr vbar_el2, x2
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mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h)
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msr spsr_el2, x2
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/* Configure GICv3 CPU interface */
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mrs x2, id_aa64pfr0_el1
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/* Extract GIC bits from the register */
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ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
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/* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
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cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
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b.ne 2f
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mrs x2, icc_sre_el2
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orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
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orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */
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msr icc_sre_el2, x2
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2:
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/* Set the address to return to our return address */
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msr elr_el2, x30
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isb
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eret
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.align 3
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.Lsctlr_res1:
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.quad SCTLR_RES1
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LEND(drop_to_el1)
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#define VECT_EMPTY \
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.align 7; \
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1: b 1b
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.align 11
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hyp_vectors:
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VECT_EMPTY /* Synchronous EL2t */
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VECT_EMPTY /* IRQ EL2t */
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VECT_EMPTY /* FIQ EL2t */
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VECT_EMPTY /* Error EL2t */
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VECT_EMPTY /* Synchronous EL2h */
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VECT_EMPTY /* IRQ EL2h */
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VECT_EMPTY /* FIQ EL2h */
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VECT_EMPTY /* Error EL2h */
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VECT_EMPTY /* Synchronous 64-bit EL1 */
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VECT_EMPTY /* IRQ 64-bit EL1 */
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VECT_EMPTY /* FIQ 64-bit EL1 */
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VECT_EMPTY /* Error 64-bit EL1 */
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VECT_EMPTY /* Synchronous 32-bit EL1 */
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VECT_EMPTY /* IRQ 32-bit EL1 */
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VECT_EMPTY /* FIQ 32-bit EL1 */
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VECT_EMPTY /* Error 32-bit EL1 */
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/*
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* Get the delta between the physical address we were loaded to and the
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* virtual address we expect to run from. This is used when building the
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* initial page table.
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*/
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LENTRY(get_virt_delta)
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/* Load the physical address of virt_map */
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adrp x29, virt_map
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add x29, x29, :lo12:virt_map
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/* Load the virtual address of virt_map stored in virt_map */
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ldr x28, [x29]
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/* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */
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sub x29, x29, x28
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/* Find the load address for the kernel */
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mov x28, #(KERNBASE)
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add x28, x28, x29
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ret
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.align 3
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virt_map:
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.quad virt_map
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LEND(get_virt_delta)
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/*
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* This builds the page tables containing the identity map, and the kernel
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* virtual map.
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*
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* It relys on:
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* We were loaded to an address that is on a 2MiB boundary
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* All the memory must not cross a 1GiB boundaty
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* x28 contains the physical address we were loaded from
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*
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* TODO: This is out of date.
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* There are at least 5 pages before that address for the page tables
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* The pages used are:
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* - The Kernel L2 table
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* - The Kernel L1 table
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* - The Kernel L0 table (TTBR1)
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* - The identity (PA = VA) L1 table
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* - The identity (PA = VA) L0 table (TTBR0)
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* - The DMAP L1 tables
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*/
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LENTRY(create_pagetables)
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/* Save the Link register */
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mov x5, x30
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/* Clean the page table */
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adrp x6, pagetable
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add x6, x6, :lo12:pagetable
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mov x26, x6
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adrp x27, pagetable_end
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add x27, x27, :lo12:pagetable_end
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1:
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stp xzr, xzr, [x6], #16
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stp xzr, xzr, [x6], #16
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stp xzr, xzr, [x6], #16
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stp xzr, xzr, [x6], #16
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cmp x6, x27
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b.lo 1b
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/*
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* Build the TTBR1 maps.
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*/
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/* Find the size of the kernel */
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mov x6, #(KERNBASE)
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#if defined(LINUX_BOOT_ABI)
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/* X19 is used as 'map FDT data' flag */
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mov x19, xzr
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/* No modules or FDT pointer ? */
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cbz x0, booti_no_fdt
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/*
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* Test if x0 points to modules descriptor(virtual address) or
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* to FDT (physical address)
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*/
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cmp x0, x6 /* x6 is #(KERNBASE) */
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b.lo booti_fdt
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#endif
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/* Booted with modules pointer */
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/* Find modulep - begin */
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sub x8, x0, x6
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/* Add two 2MiB pages for the module data and round up */
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ldr x7, =(3 * L2_SIZE - 1)
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add x8, x8, x7
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b common
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#if defined(LINUX_BOOT_ABI)
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booti_fdt:
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/* Booted by U-Boot booti with FDT data */
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/* Set 'map FDT data' flag */
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mov x19, #1
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booti_no_fdt:
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/* Booted by U-Boot booti without FTD data */
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/* Find the end - begin */
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ldr x7, .Lend
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sub x8, x7, x6
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/*
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* Add one 2MiB page for copy of FDT data (maximum FDT size),
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* one for metadata and round up
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*/
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ldr x7, =(3 * L2_SIZE - 1)
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add x8, x8, x7
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#endif
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common:
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/* Get the number of l2 pages to allocate, rounded down */
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lsr x10, x8, #(L2_SHIFT)
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/* Create the kernel space L2 table */
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mov x6, x26
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mov x7, #VM_MEMATTR_WRITE_BACK
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mov x8, #(KERNBASE & L2_BLOCK_MASK)
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mov x9, x28
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bl build_l2_block_pagetable
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/* Move to the l1 table */
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add x26, x26, #PAGE_SIZE
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/* Link the l1 -> l2 table */
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mov x9, x6
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mov x6, x26
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bl link_l1_pagetable
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/* Move to the l0 table */
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add x24, x26, #PAGE_SIZE
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/* Link the l0 -> l1 table */
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mov x9, x6
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mov x6, x24
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mov x10, #1
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bl link_l0_pagetable
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/* Link the DMAP tables */
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ldr x8, =DMAP_MIN_ADDRESS
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adrp x9, pagetable_dmap
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add x9, x9, :lo12:pagetable_dmap
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mov x10, #DMAP_TABLES
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bl link_l0_pagetable
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/*
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* Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG.
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* They are only needed early on, so the VA = PA map is uncached.
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*/
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add x27, x24, #PAGE_SIZE
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mov x6, x27 /* The initial page table */
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#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
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/* Create a table for the UART */
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mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE))
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mov x8, #(SOCDEV_VA) /* VA start */
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mov x9, #(SOCDEV_PA) /* PA start */
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mov x10, #1
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bl build_l1_block_pagetable
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#endif
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#if defined(LINUX_BOOT_ABI)
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/* Map FDT data ? */
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cbz x19, 1f
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/* Create the identity mapping for FDT data (2 MiB max) */
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mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
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mov x9, x0
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mov x8, x0 /* VA start (== PA start) */
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mov x10, #1
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bl build_l1_block_pagetable
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1:
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#endif
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/* Create the VA = PA map */
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mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
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mov x9, x28
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mov x8, x9 /* VA start (== PA start) */
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mov x10, #1
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bl build_l1_block_pagetable
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/* Move to the l0 table */
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add x27, x27, #PAGE_SIZE
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/* Link the l0 -> l1 table */
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mov x9, x6
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mov x6, x27
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mov x10, #1
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bl link_l0_pagetable
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/* Restore the Link register */
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mov x30, x5
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ret
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LEND(create_pagetables)
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/*
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* Builds an L0 -> L1 table descriptor
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*
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* This is a link for a 512GiB block of memory with up to 1GiB regions mapped
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* within it by build_l1_block_pagetable.
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*
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* x6 = L0 table
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* x8 = Virtual Address
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* x9 = L1 PA (trashed)
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* x10 = Entry count
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* x11, x12 and x13 are trashed
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*/
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LENTRY(link_l0_pagetable)
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/*
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* Link an L0 -> L1 table entry.
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*/
|
|
/* Find the table index */
|
|
lsr x11, x8, #L0_SHIFT
|
|
and x11, x11, #L0_ADDR_MASK
|
|
|
|
/* Build the L0 block entry */
|
|
mov x12, #L0_TABLE
|
|
|
|
/* Only use the output address bits */
|
|
lsr x9, x9, #PAGE_SHIFT
|
|
1: orr x13, x12, x9, lsl #PAGE_SHIFT
|
|
|
|
/* Store the entry */
|
|
str x13, [x6, x11, lsl #3]
|
|
|
|
sub x10, x10, #1
|
|
add x11, x11, #1
|
|
add x9, x9, #1
|
|
cbnz x10, 1b
|
|
|
|
ret
|
|
LEND(link_l0_pagetable)
|
|
|
|
/*
|
|
* Builds an L1 -> L2 table descriptor
|
|
*
|
|
* This is a link for a 1GiB block of memory with up to 2MiB regions mapped
|
|
* within it by build_l2_block_pagetable.
|
|
*
|
|
* x6 = L1 table
|
|
* x8 = Virtual Address
|
|
* x9 = L2 PA (trashed)
|
|
* x11, x12 and x13 are trashed
|
|
*/
|
|
LENTRY(link_l1_pagetable)
|
|
/*
|
|
* Link an L1 -> L2 table entry.
|
|
*/
|
|
/* Find the table index */
|
|
lsr x11, x8, #L1_SHIFT
|
|
and x11, x11, #Ln_ADDR_MASK
|
|
|
|
/* Build the L1 block entry */
|
|
mov x12, #L1_TABLE
|
|
|
|
/* Only use the output address bits */
|
|
lsr x9, x9, #PAGE_SHIFT
|
|
orr x13, x12, x9, lsl #PAGE_SHIFT
|
|
|
|
/* Store the entry */
|
|
str x13, [x6, x11, lsl #3]
|
|
|
|
ret
|
|
LEND(link_l1_pagetable)
|
|
|
|
/*
|
|
* Builds count 1 GiB page table entry
|
|
* x6 = L1 table
|
|
* x7 = Variable lower block attributes
|
|
* x8 = VA start
|
|
* x9 = PA start (trashed)
|
|
* x10 = Entry count
|
|
* x11, x12 and x13 are trashed
|
|
*/
|
|
LENTRY(build_l1_block_pagetable)
|
|
/*
|
|
* Build the L1 table entry.
|
|
*/
|
|
/* Find the table index */
|
|
lsr x11, x8, #L1_SHIFT
|
|
and x11, x11, #Ln_ADDR_MASK
|
|
|
|
/* Build the L1 block entry */
|
|
orr x12, x7, #L1_BLOCK
|
|
orr x12, x12, #(ATTR_DEFAULT)
|
|
|
|
/* Only use the output address bits */
|
|
lsr x9, x9, #L1_SHIFT
|
|
|
|
/* Set the physical address for this virtual address */
|
|
1: orr x13, x12, x9, lsl #L1_SHIFT
|
|
|
|
/* Store the entry */
|
|
str x13, [x6, x11, lsl #3]
|
|
|
|
sub x10, x10, #1
|
|
add x11, x11, #1
|
|
add x9, x9, #1
|
|
cbnz x10, 1b
|
|
|
|
ret
|
|
LEND(build_l1_block_pagetable)
|
|
|
|
/*
|
|
* Builds count 2 MiB page table entry
|
|
* x6 = L2 table
|
|
* x7 = Type (0 = Device, 1 = Normal)
|
|
* x8 = VA start
|
|
* x9 = PA start (trashed)
|
|
* x10 = Entry count
|
|
* x11, x12 and x13 are trashed
|
|
*/
|
|
LENTRY(build_l2_block_pagetable)
|
|
/*
|
|
* Build the L2 table entry.
|
|
*/
|
|
/* Find the table index */
|
|
lsr x11, x8, #L2_SHIFT
|
|
and x11, x11, #Ln_ADDR_MASK
|
|
|
|
/* Build the L2 block entry */
|
|
lsl x12, x7, #2
|
|
orr x12, x12, #L2_BLOCK
|
|
orr x12, x12, #(ATTR_DEFAULT)
|
|
orr x12, x12, #(ATTR_S1_UXN)
|
|
|
|
/* Only use the output address bits */
|
|
lsr x9, x9, #L2_SHIFT
|
|
|
|
/* Set the physical address for this virtual address */
|
|
1: orr x13, x12, x9, lsl #L2_SHIFT
|
|
|
|
/* Store the entry */
|
|
str x13, [x6, x11, lsl #3]
|
|
|
|
sub x10, x10, #1
|
|
add x11, x11, #1
|
|
add x9, x9, #1
|
|
cbnz x10, 1b
|
|
|
|
ret
|
|
LEND(build_l2_block_pagetable)
|
|
|
|
LENTRY(start_mmu)
|
|
dsb sy
|
|
|
|
/* Load the exception vectors */
|
|
ldr x2, =exception_vectors
|
|
msr vbar_el1, x2
|
|
|
|
/* Load ttbr0 and ttbr1 */
|
|
msr ttbr0_el1, x27
|
|
msr ttbr1_el1, x24
|
|
isb
|
|
|
|
/* Clear the Monitor Debug System control register */
|
|
msr mdscr_el1, xzr
|
|
|
|
/* Invalidate the TLB */
|
|
tlbi vmalle1is
|
|
dsb ish
|
|
isb
|
|
|
|
ldr x2, mair
|
|
msr mair_el1, x2
|
|
|
|
/*
|
|
* Setup TCR according to the PARange and ASIDBits fields
|
|
* from ID_AA64MMFR0_EL1 and the HAFDBS field from the
|
|
* ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS
|
|
* to 1 only if the ASIDBits field equals 0b0010.
|
|
*/
|
|
ldr x2, tcr
|
|
mrs x3, id_aa64mmfr0_el1
|
|
|
|
/* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */
|
|
bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH)
|
|
and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK)
|
|
|
|
/* Check if the HW supports 16 bit ASIDS */
|
|
cmp x3, #(ID_AA64MMFR0_ASIDBits_16)
|
|
/* If so x3 == 1, else x3 == 0 */
|
|
cset x3, eq
|
|
/* Set TCR.AS with x3 */
|
|
bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
|
|
|
|
/*
|
|
* Check if the HW supports access flag and dirty state updates,
|
|
* and set TCR_EL1.HA and TCR_EL1.HD accordingly.
|
|
*/
|
|
mrs x3, id_aa64mmfr1_el1
|
|
and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK)
|
|
cmp x3, #1
|
|
b.ne 1f
|
|
orr x2, x2, #(TCR_HA)
|
|
b 2f
|
|
1:
|
|
cmp x3, #2
|
|
b.ne 2f
|
|
orr x2, x2, #(TCR_HA | TCR_HD)
|
|
2:
|
|
msr tcr_el1, x2
|
|
|
|
/*
|
|
* Setup SCTLR.
|
|
*/
|
|
ldr x2, sctlr_set
|
|
ldr x3, sctlr_clear
|
|
mrs x1, sctlr_el1
|
|
bic x1, x1, x3 /* Clear the required bits */
|
|
orr x1, x1, x2 /* Set the required bits */
|
|
msr sctlr_el1, x1
|
|
isb
|
|
|
|
ret
|
|
|
|
.align 3
|
|
mair:
|
|
.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | \
|
|
MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \
|
|
MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
|
|
MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH)
|
|
tcr:
|
|
.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \
|
|
TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
|
|
sctlr_set:
|
|
/* Bits to set */
|
|
.quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
|
|
SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
|
|
SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
|
|
SCTLR_M | SCTLR_CP15BEN)
|
|
sctlr_clear:
|
|
/* Bits to clear */
|
|
.quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
|
|
SCTLR_ITD | SCTLR_A)
|
|
LEND(start_mmu)
|
|
|
|
ENTRY(abort)
|
|
b abort
|
|
END(abort)
|
|
|
|
.align 3
|
|
init_pt_va:
|
|
.quad pagetable /* XXX: Keep page tables VA */
|
|
|
|
.section .init_pagetable, "aw", %nobits
|
|
.align PAGE_SHIFT
|
|
/*
|
|
* 6 initial tables (in the following order):
|
|
* L2 for kernel (High addresses)
|
|
* L1 for kernel
|
|
* L0 for kernel
|
|
* L1 bootstrap for user (Low addresses)
|
|
* L0 bootstrap for user
|
|
* L0 for user
|
|
*/
|
|
pagetable:
|
|
.space PAGE_SIZE
|
|
pagetable_l1_ttbr1:
|
|
.space PAGE_SIZE
|
|
pagetable_l0_ttbr1:
|
|
.space PAGE_SIZE
|
|
pagetable_l1_ttbr0_bootstrap:
|
|
.space PAGE_SIZE
|
|
pagetable_l0_ttbr0_boostrap:
|
|
.space PAGE_SIZE
|
|
pagetable_l0_ttbr0:
|
|
.space PAGE_SIZE
|
|
|
|
.globl pagetable_dmap
|
|
pagetable_dmap:
|
|
.space PAGE_SIZE * DMAP_TABLES
|
|
pagetable_end:
|
|
|
|
el2_pagetable:
|
|
.space PAGE_SIZE
|
|
|
|
.globl init_pt_va
|
|
|
|
.align 4
|
|
initstack:
|
|
.space (PAGE_SIZE * KSTACK_PAGES)
|
|
initstack_end:
|
|
|
|
|
|
ENTRY(sigcode)
|
|
mov x0, sp
|
|
add x0, x0, #SF_UC
|
|
|
|
1:
|
|
mov x8, #SYS_sigreturn
|
|
svc 0
|
|
|
|
/* sigreturn failed, exit */
|
|
mov x8, #SYS_exit
|
|
svc 0
|
|
|
|
b 1b
|
|
END(sigcode)
|
|
/* This may be copied to the stack, keep it 16-byte aligned */
|
|
.align 3
|
|
esigcode:
|
|
|
|
.data
|
|
.align 3
|
|
.global szsigcode
|
|
szsigcode:
|
|
.quad esigcode - sigcode
|
|
|
|
ENTRY(aarch32_sigcode)
|
|
.word 0xe1a0000d // mov r0, sp
|
|
.word 0xe2800040 // add r0, r0, #SIGF_UC
|
|
.word 0xe59f700c // ldr r7, [pc, #12]
|
|
.word 0xef000000 // swi #0
|
|
.word 0xe59f7008 // ldr r7, [pc, #8]
|
|
.word 0xef000000 // swi #0
|
|
.word 0xeafffffa // b . - 16
|
|
END(aarch32_sigcode)
|
|
.word SYS_sigreturn
|
|
.word SYS_exit
|
|
.align 3
|
|
aarch32_esigcode:
|
|
.data
|
|
.global sz_aarch32_sigcode
|
|
sz_aarch32_sigcode:
|
|
.quad aarch32_esigcode - aarch32_sigcode
|