mirror of https://github.com/F-Stack/f-stack.git
61 lines
2.5 KiB
Plaintext
61 lines
2.5 KiB
Plaintext
; SPDX-License-Identifier: BSD-3-Clause
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; Copyright(c) 2010-2018 Intel Corporation
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; _______________
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; LINK0 RXQ0 --->| |---> LINK0 TXQ0
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; | |
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; LINK1 RXQ0 --->| |---> LINK1 TXQ0
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; | Routing |
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; LINK2 RXQ0 --->| |---> LINK2 TXQ0
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; | |
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; LINK3 RXQ0 --->| |---> LINK3 TXQ0
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; |_______________|
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; |
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; +-----------> SINK0 (route miss)
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;
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; Input packet: Ethernet/IPv4
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;
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; Packet buffer layout:
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; # Field Name Offset (Bytes) Size (Bytes)
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; 0 Mbuf 0 128
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; 1 Headroom 128 128
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; 2 Ethernet header 256 14
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; 3 IPv4 header 270 20
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mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
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link LINK0 dev 0000:02:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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link LINK1 dev 0000:02:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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link LINK2 dev 0000:06:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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link LINK3 dev 0000:06:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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table action profile AP0 ipv4 offset 270 fwd encap ether
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pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0
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pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0
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pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0
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pipeline PIPELINE0 port out bsz 32 link LINK1 txq 0
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pipeline PIPELINE0 port out bsz 32 link LINK2 txq 0
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pipeline PIPELINE0 port out bsz 32 link LINK3 txq 0
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pipeline PIPELINE0 port out bsz 32 sink
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pipeline PIPELINE0 table match lpm ipv4 offset 286 size 4K action AP0
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pipeline PIPELINE0 port in 0 table 0
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pipeline PIPELINE0 port in 1 table 0
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pipeline PIPELINE0 port in 2 table 0
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pipeline PIPELINE0 port in 3 table 0
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thread 1 pipeline PIPELINE0 enable
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pipeline PIPELINE0 table 0 rule add match default action fwd port 4
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pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.0.0.0 10 action fwd port 0 encap ether a0:a1:a2:a3:a4:a5 00:01:02:03:04:05
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pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.64.0.0 10 action fwd port 1 encap ether b0:b1:b2:b3:b4:b5 10:11:12:13:14:15
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pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.128.0.0 10 action fwd port 2 encap ether c0:c1:c2:c3:c4:c5 20:21:22:23:24:25
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pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.192.0.0 10 action fwd port 3 encap ether d0:d1:d2:d3:d4:d5 30:31:32:33:34:35
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