mirror of https://github.com/F-Stack/f-stack.git
747 lines
19 KiB
C
747 lines
19 KiB
C
/*-
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* Copyright (c) 1998-2003 Poul-Henning Kamp
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_compat.h"
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#include "opt_clock.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/limits.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/kernel.h>
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#include <sys/power.h>
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#include <sys/smp.h>
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#include <sys/vdso.h>
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#include <machine/clock.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <x86/vmware.h>
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#include "cpufreq_if.h"
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uint64_t tsc_freq;
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int tsc_is_invariant;
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int tsc_perf_stat;
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static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag;
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SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN,
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&tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant");
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#ifdef SMP
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int smp_tsc;
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SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0,
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"Indicates whether the TSC is safe to use in SMP mode");
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int smp_tsc_adjust = 0;
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SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN,
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&smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP");
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#endif
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static int tsc_shift = 1;
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SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN,
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&tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency");
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static int tsc_disabled;
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SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0,
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"Disable x86 Time Stamp Counter");
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static int tsc_skip_calibration;
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SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN,
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&tsc_skip_calibration, 0, "Disable TSC frequency calibration");
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static void tsc_freq_changed(void *arg, const struct cf_level *level,
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int status);
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static void tsc_freq_changing(void *arg, const struct cf_level *level,
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int *status);
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static unsigned tsc_get_timecount(struct timecounter *tc);
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static inline unsigned tsc_get_timecount_low(struct timecounter *tc);
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static unsigned tsc_get_timecount_lfence(struct timecounter *tc);
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static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc);
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static unsigned tsc_get_timecount_mfence(struct timecounter *tc);
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static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc);
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static void tsc_levels_changed(void *arg, int unit);
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static struct timecounter tsc_timecounter = {
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tsc_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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0, /* frequency */
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"TSC", /* name */
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800, /* quality (adjusted in code) */
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};
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static void
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tsc_freq_vmware(void)
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{
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u_int regs[4];
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if (hv_high >= 0x40000010) {
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do_cpuid(0x40000010, regs);
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tsc_freq = regs[0] * 1000;
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} else {
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vmware_hvcall(VMW_HVCMD_GETHZ, regs);
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if (regs[1] != UINT_MAX)
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tsc_freq = regs[0] | ((uint64_t)regs[1] << 32);
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}
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tsc_is_invariant = 1;
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}
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static void
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tsc_freq_intel(void)
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{
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char brand[48];
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u_int regs[4];
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uint64_t freq;
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char *p;
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u_int i;
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/*
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* Intel Processor Identification and the CPUID Instruction
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* Application Note 485.
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* http://www.intel.com/assets/pdf/appnote/241618.pdf
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*/
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if (cpu_exthigh >= 0x80000004) {
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p = brand;
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for (i = 0x80000002; i < 0x80000005; i++) {
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do_cpuid(i, regs);
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memcpy(p, regs, sizeof(regs));
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p += sizeof(regs);
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}
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p = NULL;
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for (i = 0; i < sizeof(brand) - 1; i++)
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if (brand[i] == 'H' && brand[i + 1] == 'z')
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p = brand + i;
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if (p != NULL) {
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p -= 5;
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switch (p[4]) {
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case 'M':
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i = 1;
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break;
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case 'G':
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i = 1000;
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break;
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case 'T':
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i = 1000000;
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break;
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default:
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return;
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}
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#define C2D(c) ((c) - '0')
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if (p[1] == '.') {
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freq = C2D(p[0]) * 1000;
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freq += C2D(p[2]) * 100;
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freq += C2D(p[3]) * 10;
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freq *= i * 1000;
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} else {
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freq = C2D(p[0]) * 1000;
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freq += C2D(p[1]) * 100;
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freq += C2D(p[2]) * 10;
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freq += C2D(p[3]);
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freq *= i * 1000000;
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}
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#undef C2D
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tsc_freq = freq;
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}
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}
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}
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static void
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probe_tsc_freq(void)
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{
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u_int regs[4];
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uint64_t tsc1, tsc2;
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if (cpu_high >= 6) {
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do_cpuid(6, regs);
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if ((regs[2] & CPUID_PERF_STAT) != 0) {
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/*
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* XXX Some emulators expose host CPUID without actual
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* support for these MSRs. We must test whether they
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* really work.
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*/
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wrmsr(MSR_MPERF, 0);
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wrmsr(MSR_APERF, 0);
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DELAY(10);
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if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
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tsc_perf_stat = 1;
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}
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}
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if (vm_guest == VM_GUEST_VMWARE) {
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tsc_freq_vmware();
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return;
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}
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
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(vm_guest == VM_GUEST_NO &&
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CPUID_TO_FAMILY(cpu_id) >= 0x10))
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tsc_is_invariant = 1;
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if (cpu_feature & CPUID_SSE2) {
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tsc_timecounter.tc_get_timecount =
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tsc_get_timecount_mfence;
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}
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break;
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case CPU_VENDOR_INTEL:
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if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
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(vm_guest == VM_GUEST_NO &&
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((CPUID_TO_FAMILY(cpu_id) == 0x6 &&
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CPUID_TO_MODEL(cpu_id) >= 0xe) ||
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(CPUID_TO_FAMILY(cpu_id) == 0xf &&
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CPUID_TO_MODEL(cpu_id) >= 0x3))))
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tsc_is_invariant = 1;
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if (cpu_feature & CPUID_SSE2) {
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tsc_timecounter.tc_get_timecount =
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tsc_get_timecount_lfence;
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}
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break;
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case CPU_VENDOR_CENTAUR:
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if (vm_guest == VM_GUEST_NO &&
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CPUID_TO_FAMILY(cpu_id) == 0x6 &&
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CPUID_TO_MODEL(cpu_id) >= 0xf &&
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(rdmsr(0x1203) & 0x100000000ULL) == 0)
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tsc_is_invariant = 1;
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if (cpu_feature & CPUID_SSE2) {
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tsc_timecounter.tc_get_timecount =
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tsc_get_timecount_lfence;
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}
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break;
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}
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if (tsc_skip_calibration) {
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if (cpu_vendor_id == CPU_VENDOR_INTEL)
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tsc_freq_intel();
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return;
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}
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if (bootverbose)
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printf("Calibrating TSC clock ... ");
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tsc1 = rdtsc();
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DELAY(1000000);
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tsc2 = rdtsc();
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tsc_freq = tsc2 - tsc1;
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if (bootverbose)
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printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq);
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}
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void
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init_TSC(void)
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{
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if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
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return;
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#ifdef __i386__
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/* The TSC is known to be broken on certain CPUs. */
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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switch (cpu_id & 0xFF0) {
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case 0x500:
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/* K5 Model 0 */
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return;
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}
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break;
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case CPU_VENDOR_CENTAUR:
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switch (cpu_id & 0xff0) {
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case 0x540:
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/*
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* http://www.centtech.com/c6_data_sheet.pdf
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*
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* I-12 RDTSC may return incoherent values in EDX:EAX
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* I-13 RDTSC hangs when certain event counters are used
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*/
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return;
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}
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break;
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case CPU_VENDOR_NSC:
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switch (cpu_id & 0xff0) {
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case 0x540:
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if ((cpu_id & CPUID_STEPPING) == 0)
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return;
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break;
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}
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break;
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}
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#endif
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probe_tsc_freq();
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/*
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* Inform CPU accounting about our boot-time clock rate. This will
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* be updated if someone loads a cpufreq driver after boot that
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* discovers a new max frequency.
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*/
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if (tsc_freq != 0)
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set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant);
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if (tsc_is_invariant)
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return;
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/* Register to find out about changes in CPU frequency. */
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tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change,
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tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST);
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tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
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tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST);
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tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed,
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tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY);
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}
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#ifdef SMP
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/*
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* RDTSC is not a serializing instruction, and does not drain
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* instruction stream, so we need to drain the stream before executing
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* it. It could be fixed by use of RDTSCP, except the instruction is
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* not available everywhere.
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*
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* Use CPUID for draining in the boot-time SMP constistency test. The
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* timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel
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* and VIA) when SSE2 is present, and nothing on older machines which
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* also do not issue RDTSC prematurely. There, testing for SSE2 and
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* vendor is too cumbersome, and we learn about TSC presence from CPUID.
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*
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* Do not use do_cpuid(), since we do not need CPUID results, which
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* have to be written into memory with do_cpuid().
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*/
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#define TSC_READ(x) \
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static void \
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tsc_read_##x(void *arg) \
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{ \
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uint64_t *tsc = arg; \
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u_int cpu = PCPU_GET(cpuid); \
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\
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__asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx"); \
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tsc[cpu * 3 + x] = rdtsc(); \
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}
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TSC_READ(0)
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TSC_READ(1)
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TSC_READ(2)
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#undef TSC_READ
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#define N 1000
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static void
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comp_smp_tsc(void *arg)
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{
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uint64_t *tsc;
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int64_t d1, d2;
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u_int cpu = PCPU_GET(cpuid);
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u_int i, j, size;
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size = (mp_maxid + 1) * 3;
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for (i = 0, tsc = arg; i < N; i++, tsc += size)
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CPU_FOREACH(j) {
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if (j == cpu)
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continue;
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d1 = tsc[cpu * 3 + 1] - tsc[j * 3];
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d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1];
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if (d1 <= 0 || d2 <= 0) {
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smp_tsc = 0;
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return;
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}
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}
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}
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static void
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adj_smp_tsc(void *arg)
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{
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uint64_t *tsc;
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int64_t d, min, max;
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u_int cpu = PCPU_GET(cpuid);
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u_int first, i, size;
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first = CPU_FIRST();
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if (cpu == first)
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return;
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min = INT64_MIN;
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max = INT64_MAX;
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size = (mp_maxid + 1) * 3;
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for (i = 0, tsc = arg; i < N; i++, tsc += size) {
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d = tsc[first * 3] - tsc[cpu * 3 + 1];
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if (d > min)
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min = d;
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d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2];
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if (d > min)
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min = d;
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d = tsc[first * 3 + 1] - tsc[cpu * 3];
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if (d < max)
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max = d;
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d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1];
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if (d < max)
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max = d;
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}
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if (min > max)
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return;
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d = min / 2 + max / 2;
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__asm __volatile (
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"movl $0x10, %%ecx\n\t"
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"rdmsr\n\t"
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"addl %%edi, %%eax\n\t"
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"adcl %%esi, %%edx\n\t"
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"wrmsr\n"
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: /* No output */
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: "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32))
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: "ax", "cx", "dx", "cc"
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);
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}
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static int
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test_tsc(void)
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{
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uint64_t *data, *tsc;
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u_int i, size, adj;
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if ((!smp_tsc && !tsc_is_invariant) || vm_guest)
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return (-100);
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size = (mp_maxid + 1) * 3;
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data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK);
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adj = 0;
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retry:
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for (i = 0, tsc = data; i < N; i++, tsc += size)
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smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc);
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smp_tsc = 1; /* XXX */
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smp_rendezvous(smp_no_rendevous_barrier, comp_smp_tsc,
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smp_no_rendevous_barrier, data);
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if (!smp_tsc && adj < smp_tsc_adjust) {
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adj++;
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smp_rendezvous(smp_no_rendevous_barrier, adj_smp_tsc,
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smp_no_rendevous_barrier, data);
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goto retry;
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}
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free(data, M_TEMP);
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if (bootverbose)
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printf("SMP: %sed TSC synchronization test%s\n",
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smp_tsc ? "pass" : "fail",
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adj > 0 ? " after adjustment" : "");
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if (smp_tsc && tsc_is_invariant) {
|
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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/*
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* Starting with Family 15h processors, TSC clock
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* source is in the north bridge. Check whether
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* we have a single-socket/multi-core platform.
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* XXX Need more work for complex cases.
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*/
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if (CPUID_TO_FAMILY(cpu_id) < 0x15 ||
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(amd_feature2 & AMDID2_CMP) == 0 ||
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smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1)
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break;
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return (1000);
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case CPU_VENDOR_INTEL:
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/*
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* XXX Assume Intel platforms have synchronized TSCs.
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*/
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return (1000);
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}
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return (800);
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}
|
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return (-100);
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}
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#undef N
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#else
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|
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/*
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* The function is not called, it is provided to avoid linking failure
|
|
* on uniprocessor kernel.
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|
*/
|
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static int
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test_tsc(void)
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{
|
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|
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return (0);
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}
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|
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#endif /* SMP */
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|
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static void
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|
init_TSC_tc(void)
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|
{
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|
uint64_t max_freq;
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|
int shift;
|
|
|
|
if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
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|
return;
|
|
|
|
/*
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* Limit timecounter frequency to fit in an int and prevent it from
|
|
* overflowing too fast.
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|
*/
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|
max_freq = UINT_MAX;
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|
|
|
/*
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|
* We can not use the TSC if we support APM. Precise timekeeping
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|
* on an APM'ed machine is at best a fools pursuit, since
|
|
* any and all of the time spent in various SMM code can't
|
|
* be reliably accounted for. Reading the RTC is your only
|
|
* source of reliable time info. The i8254 loses too, of course,
|
|
* but we need to have some kind of time...
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|
* We don't know at this point whether APM is going to be used
|
|
* or not, nor when it might be activated. Play it safe.
|
|
*/
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|
if (power_pm_get_type() == POWER_PM_TYPE_APM) {
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|
tsc_timecounter.tc_quality = -1000;
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|
if (bootverbose)
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|
printf("TSC timecounter disabled: APM enabled.\n");
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|
goto init;
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|
}
|
|
|
|
/*
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|
* Intel CPUs without a C-state invariant TSC can stop the TSC
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|
* in either C2 or C3. Disable use of C2 and C3 while using
|
|
* the TSC as the timecounter. The timecounter can be changed
|
|
* to enable C2 and C3.
|
|
*
|
|
* Note that the TSC is used as the cputicker for computing
|
|
* thread runtime regardless of the timecounter setting, so
|
|
* using an alternate timecounter and enabling C2 or C3 can
|
|
* result incorrect runtimes for kernel idle threads (but not
|
|
* for any non-idle threads).
|
|
*/
|
|
if (cpu_deepest_sleep >= 2 && cpu_vendor_id == CPU_VENDOR_INTEL &&
|
|
(amd_pminfo & AMDPM_TSC_INVARIANT) == 0) {
|
|
tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP;
|
|
if (bootverbose)
|
|
printf("TSC timecounter disables C2 and C3.\n");
|
|
}
|
|
|
|
/*
|
|
* We can not use the TSC in SMP mode unless the TSCs on all CPUs
|
|
* are synchronized. If the user is sure that the system has
|
|
* synchronized TSCs, set kern.timecounter.smp_tsc tunable to a
|
|
* non-zero value. The TSC seems unreliable in virtualized SMP
|
|
* environments, so it is set to a negative quality in those cases.
|
|
*/
|
|
if (mp_ncpus > 1)
|
|
tsc_timecounter.tc_quality = test_tsc();
|
|
else if (tsc_is_invariant)
|
|
tsc_timecounter.tc_quality = 1000;
|
|
max_freq >>= tsc_shift;
|
|
|
|
init:
|
|
for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++)
|
|
;
|
|
if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) {
|
|
if (cpu_vendor_id == CPU_VENDOR_AMD) {
|
|
tsc_timecounter.tc_get_timecount = shift > 0 ?
|
|
tsc_get_timecount_low_mfence :
|
|
tsc_get_timecount_mfence;
|
|
} else {
|
|
tsc_timecounter.tc_get_timecount = shift > 0 ?
|
|
tsc_get_timecount_low_lfence :
|
|
tsc_get_timecount_lfence;
|
|
}
|
|
} else {
|
|
tsc_timecounter.tc_get_timecount = shift > 0 ?
|
|
tsc_get_timecount_low : tsc_get_timecount;
|
|
}
|
|
if (shift > 0) {
|
|
tsc_timecounter.tc_name = "TSC-low";
|
|
if (bootverbose)
|
|
printf("TSC timecounter discards lower %d bit(s)\n",
|
|
shift);
|
|
}
|
|
if (tsc_freq != 0) {
|
|
tsc_timecounter.tc_frequency = tsc_freq >> shift;
|
|
tsc_timecounter.tc_priv = (void *)(intptr_t)shift;
|
|
tc_init(&tsc_timecounter);
|
|
}
|
|
}
|
|
SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL);
|
|
|
|
/*
|
|
* When cpufreq levels change, find out about the (new) max frequency. We
|
|
* use this to update CPU accounting in case it got a lower estimate at boot.
|
|
*/
|
|
static void
|
|
tsc_levels_changed(void *arg, int unit)
|
|
{
|
|
device_t cf_dev;
|
|
struct cf_level *levels;
|
|
int count, error;
|
|
uint64_t max_freq;
|
|
|
|
/* Only use values from the first CPU, assuming all are equal. */
|
|
if (unit != 0)
|
|
return;
|
|
|
|
/* Find the appropriate cpufreq device instance. */
|
|
cf_dev = devclass_get_device(devclass_find("cpufreq"), unit);
|
|
if (cf_dev == NULL) {
|
|
printf("tsc_levels_changed() called but no cpufreq device?\n");
|
|
return;
|
|
}
|
|
|
|
/* Get settings from the device and find the max frequency. */
|
|
count = 64;
|
|
levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT);
|
|
if (levels == NULL)
|
|
return;
|
|
error = CPUFREQ_LEVELS(cf_dev, levels, &count);
|
|
if (error == 0 && count != 0) {
|
|
max_freq = (uint64_t)levels[0].total_set.freq * 1000000;
|
|
set_cputicker(rdtsc, max_freq, 1);
|
|
} else
|
|
printf("tsc_levels_changed: no max freq found\n");
|
|
free(levels, M_TEMP);
|
|
}
|
|
|
|
/*
|
|
* If the TSC timecounter is in use, veto the pending change. It may be
|
|
* possible in the future to handle a dynamically-changing timecounter rate.
|
|
*/
|
|
static void
|
|
tsc_freq_changing(void *arg, const struct cf_level *level, int *status)
|
|
{
|
|
|
|
if (*status != 0 || timecounter != &tsc_timecounter)
|
|
return;
|
|
|
|
printf("timecounter TSC must not be in use when "
|
|
"changing frequencies; change denied\n");
|
|
*status = EBUSY;
|
|
}
|
|
|
|
/* Update TSC freq with the value indicated by the caller. */
|
|
static void
|
|
tsc_freq_changed(void *arg, const struct cf_level *level, int status)
|
|
{
|
|
uint64_t freq;
|
|
|
|
/* If there was an error during the transition, don't do anything. */
|
|
if (tsc_disabled || status != 0)
|
|
return;
|
|
|
|
/* Total setting for this level gives the new frequency in MHz. */
|
|
freq = (uint64_t)level->total_set.freq * 1000000;
|
|
atomic_store_rel_64(&tsc_freq, freq);
|
|
tsc_timecounter.tc_frequency =
|
|
freq >> (int)(intptr_t)tsc_timecounter.tc_priv;
|
|
}
|
|
|
|
static int
|
|
sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
int error;
|
|
uint64_t freq;
|
|
|
|
freq = atomic_load_acq_64(&tsc_freq);
|
|
if (freq == 0)
|
|
return (EOPNOTSUPP);
|
|
error = sysctl_handle_64(oidp, &freq, 0, req);
|
|
if (error == 0 && req->newptr != NULL) {
|
|
atomic_store_rel_64(&tsc_freq, freq);
|
|
atomic_store_rel_64(&tsc_timecounter.tc_frequency,
|
|
freq >> (int)(intptr_t)tsc_timecounter.tc_priv);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_U64 | CTLFLAG_RW,
|
|
0, 0, sysctl_machdep_tsc_freq, "QU", "Time Stamp Counter frequency");
|
|
|
|
static u_int
|
|
tsc_get_timecount(struct timecounter *tc __unused)
|
|
{
|
|
|
|
return (rdtsc32());
|
|
}
|
|
|
|
static inline u_int
|
|
tsc_get_timecount_low(struct timecounter *tc)
|
|
{
|
|
uint32_t rv;
|
|
|
|
__asm __volatile("rdtsc; shrd %%cl, %%edx, %0"
|
|
: "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx");
|
|
return (rv);
|
|
}
|
|
|
|
static u_int
|
|
tsc_get_timecount_lfence(struct timecounter *tc __unused)
|
|
{
|
|
|
|
lfence();
|
|
return (rdtsc32());
|
|
}
|
|
|
|
static u_int
|
|
tsc_get_timecount_low_lfence(struct timecounter *tc)
|
|
{
|
|
|
|
lfence();
|
|
return (tsc_get_timecount_low(tc));
|
|
}
|
|
|
|
static u_int
|
|
tsc_get_timecount_mfence(struct timecounter *tc __unused)
|
|
{
|
|
|
|
mfence();
|
|
return (rdtsc32());
|
|
}
|
|
|
|
static u_int
|
|
tsc_get_timecount_low_mfence(struct timecounter *tc)
|
|
{
|
|
|
|
mfence();
|
|
return (tsc_get_timecount_low(tc));
|
|
}
|
|
|
|
uint32_t
|
|
cpu_fill_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
|
|
{
|
|
|
|
vdso_th->th_x86_shift = (int)(intptr_t)tc->tc_priv;
|
|
bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
|
|
return (tc == &tsc_timecounter);
|
|
}
|
|
|
|
#ifdef COMPAT_FREEBSD32
|
|
uint32_t
|
|
cpu_fill_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
|
|
struct timecounter *tc)
|
|
{
|
|
|
|
vdso_th32->th_x86_shift = (int)(intptr_t)tc->tc_priv;
|
|
bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));
|
|
return (tc == &tsc_timecounter);
|
|
}
|
|
#endif
|