mirror of https://github.com/F-Stack/f-stack.git
267 lines
8.3 KiB
C
267 lines
8.3 KiB
C
/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _LIO_HW_DEFS_H_
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#define _LIO_HW_DEFS_H_
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#include <rte_io.h>
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#ifndef PCI_VENDOR_ID_CAVIUM
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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#endif
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#define LIO_CN23XX_VF_VID 0x9712
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/* CN23xx subsystem device ids */
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#define PCI_SUBSYS_DEV_ID_CN2350_210 0x0004
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#define PCI_SUBSYS_DEV_ID_CN2360_210 0x0005
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#define PCI_SUBSYS_DEV_ID_CN2360_225 0x0006
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#define PCI_SUBSYS_DEV_ID_CN2350_225 0x0007
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#define PCI_SUBSYS_DEV_ID_CN2350_210SVPN3 0x0008
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#define PCI_SUBSYS_DEV_ID_CN2360_210SVPN3 0x0009
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#define PCI_SUBSYS_DEV_ID_CN2350_210SVPT 0x000a
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#define PCI_SUBSYS_DEV_ID_CN2360_210SVPT 0x000b
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/* --------------------------CONFIG VALUES------------------------ */
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/* CN23xx IQ configuration macros */
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#define CN23XX_MAX_RINGS_PER_PF 64
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#define CN23XX_MAX_RINGS_PER_VF 8
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#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
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#define CN23XX_MAX_IQ_DESCRIPTORS 512
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#define CN23XX_MIN_IQ_DESCRIPTORS 128
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#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
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#define CN23XX_MAX_OQ_DESCRIPTORS 512
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#define CN23XX_MIN_OQ_DESCRIPTORS 128
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#define CN23XX_OQ_BUF_SIZE 1536
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#define CN23XX_OQ_REFIL_THRESHOLD 16
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#define CN23XX_DEFAULT_NUM_PORTS 1
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#define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
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/* common OCTEON configuration macros */
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#define OCTEON_64BYTE_INSTR 64
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#define OCTEON_OQ_INFOPTR_MODE 1
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/* Max IOQs per LIO Link */
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#define LIO_MAX_IOQS_PER_IF 64
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/* Wait time in milliseconds for FLR */
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#define LIO_PCI_FLR_WAIT 100
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enum lio_card_type {
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LIO_23XX /* 23xx */
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};
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#define LIO_23XX_NAME "23xx"
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#define LIO_DEV_RUNNING 0xc
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#define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \
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((cfg)->default_config->oq.refill_threshold)
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#define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
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((cfg)->default_config->num_def_tx_descs)
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#define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
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/* The following config values are fixed and should not be modified. */
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/* Maximum number of Instruction queues */
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#define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
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#define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
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#define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
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#define LIO_DEVICE_NAME_LEN 32
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#define LIO_BASE_MAJOR_VERSION 1
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#define LIO_BASE_MINOR_VERSION 5
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#define LIO_BASE_MICRO_VERSION 1
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#define LIO_FW_VERSION_LENGTH 32
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#define LIO_VF_TRUST_MIN_VERSION "1.7.1"
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/** Tag types used by Octeon cores in its work. */
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enum octeon_tag_type {
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OCTEON_ORDERED_TAG = 0,
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OCTEON_ATOMIC_TAG = 1,
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};
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/* pre-defined host->NIC tag values */
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#define LIO_CONTROL (0x11111110)
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#define LIO_DATA(i) (0x11111111 + (i))
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/* used for NIC operations */
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#define LIO_OPCODE 1
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/* Subcodes are used by host driver/apps to identify the sub-operation
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* for the core. They only need to by unique for a given subsystem.
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*/
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#define LIO_OPCODE_SUBCODE(op, sub) \
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((((op) & 0x0f) << 8) | ((sub) & 0x7f))
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/** LIO_OPCODE subcodes */
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/* This subcode is sent by core PCI driver to indicate cores are ready. */
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#define LIO_OPCODE_NW_DATA 0x02 /* network packet data */
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#define LIO_OPCODE_CMD 0x03
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#define LIO_OPCODE_INFO 0x04
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#define LIO_OPCODE_PORT_STATS 0x05
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#define LIO_OPCODE_IF_CFG 0x09
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#define LIO_MIN_RX_BUF_SIZE 64
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#define LIO_MAX_RX_PKTLEN (64 * 1024)
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/* NIC Command types */
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#define LIO_CMD_CHANGE_MTU 0x1
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#define LIO_CMD_CHANGE_DEVFLAGS 0x3
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#define LIO_CMD_RX_CTL 0x4
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#define LIO_CMD_CLEAR_STATS 0x6
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#define LIO_CMD_SET_RSS 0xD
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#define LIO_CMD_TNL_RX_CSUM_CTL 0x10
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#define LIO_CMD_TNL_TX_CSUM_CTL 0x11
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#define LIO_CMD_ADD_VLAN_FILTER 0x17
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#define LIO_CMD_DEL_VLAN_FILTER 0x18
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#define LIO_CMD_VXLAN_PORT_CONFIG 0x19
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#define LIO_CMD_VXLAN_PORT_ADD 0x0
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#define LIO_CMD_VXLAN_PORT_DEL 0x1
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#define LIO_CMD_RXCSUM_ENABLE 0x0
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#define LIO_CMD_TXCSUM_ENABLE 0x0
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/* RX(packets coming from wire) Checksum verification flags */
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/* TCP/UDP csum */
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#define LIO_L4_CSUM_VERIFIED 0x1
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#define LIO_IP_CSUM_VERIFIED 0x2
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/* RSS */
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#define LIO_RSS_PARAM_DISABLE_RSS 0x10
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#define LIO_RSS_PARAM_HASH_KEY_UNCHANGED 0x08
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#define LIO_RSS_PARAM_ITABLE_UNCHANGED 0x04
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#define LIO_RSS_PARAM_HASH_INFO_UNCHANGED 0x02
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#define LIO_RSS_HASH_IPV4 0x100
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#define LIO_RSS_HASH_TCP_IPV4 0x200
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#define LIO_RSS_HASH_IPV6 0x400
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#define LIO_RSS_HASH_TCP_IPV6 0x1000
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#define LIO_RSS_HASH_IPV6_EX 0x800
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#define LIO_RSS_HASH_TCP_IPV6_EX 0x2000
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#define LIO_RSS_OFFLOAD_ALL ( \
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LIO_RSS_HASH_IPV4 | \
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LIO_RSS_HASH_TCP_IPV4 | \
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LIO_RSS_HASH_IPV6 | \
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LIO_RSS_HASH_TCP_IPV6 | \
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LIO_RSS_HASH_IPV6_EX | \
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LIO_RSS_HASH_TCP_IPV6_EX)
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#define LIO_RSS_MAX_TABLE_SZ 128
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#define LIO_RSS_MAX_KEY_SZ 40
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#define LIO_RSS_PARAM_SIZE 16
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/* Interface flags communicated between host driver and core app. */
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enum lio_ifflags {
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LIO_IFFLAG_PROMISC = 0x01,
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LIO_IFFLAG_ALLMULTI = 0x02,
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LIO_IFFLAG_UNICAST = 0x10
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};
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/* Routines for reading and writing CSRs */
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#ifdef RTE_LIBRTE_LIO_DEBUG_REGS
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#define lio_write_csr(lio_dev, reg_off, value) \
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do { \
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typeof(lio_dev) _dev = lio_dev; \
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typeof(reg_off) _reg_off = reg_off; \
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typeof(value) _value = value; \
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PMD_REGS_LOG(_dev, \
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"Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
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(unsigned long)_reg_off, \
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(unsigned long)_value); \
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rte_write32(_value, _dev->hw_addr + _reg_off); \
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} while (0)
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#define lio_write_csr64(lio_dev, reg_off, val64) \
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do { \
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typeof(lio_dev) _dev = lio_dev; \
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typeof(reg_off) _reg_off = reg_off; \
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typeof(val64) _val64 = val64; \
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PMD_REGS_LOG( \
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_dev, \
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"Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
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(unsigned long)_reg_off, \
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(unsigned long long)_val64); \
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rte_write64(_val64, _dev->hw_addr + _reg_off); \
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} while (0)
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#define lio_read_csr(lio_dev, reg_off) \
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({ \
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typeof(lio_dev) _dev = lio_dev; \
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typeof(reg_off) _reg_off = reg_off; \
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uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
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PMD_REGS_LOG(_dev, \
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"Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
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(unsigned long)_reg_off, \
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(unsigned long)val); \
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val; \
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})
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#define lio_read_csr64(lio_dev, reg_off) \
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({ \
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typeof(lio_dev) _dev = lio_dev; \
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typeof(reg_off) _reg_off = reg_off; \
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uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
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PMD_REGS_LOG( \
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_dev, \
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"Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
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(unsigned long)_reg_off, \
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(unsigned long long)val64); \
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val64; \
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})
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#else
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#define lio_write_csr(lio_dev, reg_off, value) \
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rte_write32(value, (lio_dev)->hw_addr + (reg_off))
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#define lio_write_csr64(lio_dev, reg_off, val64) \
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rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
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#define lio_read_csr(lio_dev, reg_off) \
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rte_read32((lio_dev)->hw_addr + (reg_off))
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#define lio_read_csr64(lio_dev, reg_off) \
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rte_read64((lio_dev)->hw_addr + (reg_off))
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#endif
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#endif /* _LIO_HW_DEFS_H_ */
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