mirror of https://github.com/F-Stack/f-stack.git
197 lines
6.0 KiB
C
197 lines
6.0 KiB
C
/*
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* Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*
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* Copyright (c) 2014, Cisco Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef _VNIC_WQ_H_
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#define _VNIC_WQ_H_
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#include "vnic_dev.h"
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#include "vnic_cq.h"
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#include <rte_memzone.h>
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/* Work queue control */
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struct vnic_wq_ctrl {
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u64 ring_base; /* 0x00 */
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u32 ring_size; /* 0x08 */
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u32 pad0;
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u32 posted_index; /* 0x10 */
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u32 pad1;
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u32 cq_index; /* 0x18 */
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u32 pad2;
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u32 enable; /* 0x20 */
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u32 pad3;
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u32 running; /* 0x28 */
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u32 pad4;
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u32 fetch_index; /* 0x30 */
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u32 pad5;
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u32 dca_value; /* 0x38 */
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u32 pad6;
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u32 error_interrupt_enable; /* 0x40 */
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u32 pad7;
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u32 error_interrupt_offset; /* 0x48 */
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u32 pad8;
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u32 error_status; /* 0x50 */
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u32 pad9;
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};
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/* 16 bytes */
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struct vnic_wq_buf {
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struct rte_mempool *pool;
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void *mb;
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};
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struct vnic_wq {
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unsigned int index;
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struct vnic_dev *vdev;
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struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
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struct vnic_dev_ring ring;
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struct vnic_wq_buf *bufs;
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unsigned int head_idx;
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unsigned int tail_idx;
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unsigned int socket_id;
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const struct rte_memzone *cqmsg_rz;
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uint16_t last_completed_index;
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};
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static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
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{
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/* how many does SW own? */
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return wq->ring.desc_avail;
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}
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static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
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{
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/* how many does HW own? */
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return wq->ring.desc_count - wq->ring.desc_avail - 1;
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}
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#define PI_LOG2_CACHE_LINE_SIZE 5
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#define PI_INDEX_BITS 12
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#define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
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#define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
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#define PI_PREFETCH_LEN_OFF 16
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#define PI_PREFETCH_ADDR_BITS 43
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#define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
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#define PI_PREFETCH_ADDR_OFF 21
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/** How many cache lines are touched by buffer (addr, len). */
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static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
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unsigned int len)
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{
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const unsigned long mask = PI_PREFETCH_LEN_MASK;
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const unsigned long laddr = (unsigned long)addr;
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unsigned long lines, equiv_len;
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/* A. If addr is aligned, our solution is just to round up len to the
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next boundary.
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e.g. addr = 0, len = 48
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+--------------------+
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|XXXXXXXXXXXXXXXXXXXX| 32-byte cacheline a
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+--------------------+
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|XXXXXXXXXX | cacheline b
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+--------------------+
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B. If addr is not aligned, however, we may use an extra
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cacheline. e.g. addr = 12, len = 22
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+--------------------+
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| XXXXXXXXXXXXX|
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+--------------------+
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|XX |
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+--------------------+
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Our solution is to make the problem equivalent to case A
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above by adding the empty space in the first cacheline to the length:
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unsigned long len;
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+--------------------+
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|eeeeeeeXXXXXXXXXXXXX| "e" is empty space, which we add to len
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+--------------------+
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|XX |
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+--------------------+
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*/
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equiv_len = len + (laddr & mask);
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/* Now we can just round up this len to the next 32-byte boundary. */
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lines = (equiv_len + mask) & (~mask);
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/* Scale bytes -> cachelines. */
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return lines >> PI_LOG2_CACHE_LINE_SIZE;
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}
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static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
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unsigned int index)
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{
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unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
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/* Wish we could avoid a branch here. We could have separate
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* vnic_wq_post() and vinc_wq_post_inline(), the latter
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* only supporting < 1k (2^5 * 2^5) sends, I suppose. This would
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* eliminate the if (eop) branch as well.
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*/
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if (num_cache_lines > PI_PREFETCH_LEN_MASK)
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num_cache_lines = 0;
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return (index & PI_INDEX_MASK) |
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((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |
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(((addr >> PI_LOG2_CACHE_LINE_SIZE) &
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PI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);
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}
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static inline uint32_t
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buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
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{
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idx++;
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if (unlikely(idx == n_descriptors))
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idx = 0;
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return idx;
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}
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void vnic_wq_free(struct vnic_wq *wq);
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int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
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unsigned int desc_count, unsigned int desc_size);
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void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
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unsigned int fetch_index, unsigned int posted_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
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unsigned int vnic_wq_error_status(struct vnic_wq *wq);
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void vnic_wq_enable(struct vnic_wq *wq);
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int vnic_wq_disable(struct vnic_wq *wq);
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void vnic_wq_clean(struct vnic_wq *wq,
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void (*buf_clean)(struct vnic_wq_buf *buf));
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#endif /* _VNIC_WQ_H_ */
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