mirror of https://github.com/F-Stack/f-stack.git
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2023 Intel Corporation
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*/
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#ifndef _CPFL_RXTX_H_
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#define _CPFL_RXTX_H_
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#include <idpf_common_rxtx.h>
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#include "cpfl_ethdev.h"
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/* In QLEN must be whole number of 32 descriptors. */
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#define CPFL_ALIGN_RING_DESC 32
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#define CPFL_MIN_RING_DESC 32
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#define CPFL_MAX_RING_DESC 4096
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#define CPFL_DMA_MEM_ALIGN 4096
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#define CPFL_MAX_HAIRPINQ_RX_2_TX 1
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#define CPFL_MAX_HAIRPINQ_TX_2_RX 1
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#define CPFL_MAX_HAIRPINQ_NB_DESC 1024
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#define CPFL_MAX_P2P_NB_QUEUES 16
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#define CPFL_P2P_NB_RX_BUFQ 1
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#define CPFL_P2P_NB_TX_COMPLQ 1
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#define CPFL_P2P_NB_QUEUE_GRPS 1
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#define CPFL_P2P_QUEUE_GRP_ID 1
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#define CPFL_P2P_DESC_LEN 16
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#define CPFL_P2P_NB_MBUF 4096
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#define CPFL_P2P_CACHE_SIZE 250
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#define CPFL_P2P_MBUF_SIZE 2048
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#define CPFL_P2P_RING_BUF 128
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/* Base address of the HW descriptor ring should be 128B aligned. */
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#define CPFL_RING_BASE_ALIGN 128
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#define CPFL_DEFAULT_RX_FREE_THRESH 32
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#define CPFL_RXBUF_LOW_WATERMARK 64
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#define CPFL_DEFAULT_TX_RS_THRESH 32
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#define CPFL_DEFAULT_TX_FREE_THRESH 32
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#define CPFL_SUPPORT_CHAIN_NUM 5
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#define CPFL_RX_BUF_STRIDE 64
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/* The value written in the RX buffer queue tail register,
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* and in WritePTR field in the TX completion queue context,
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* must be a multiple of 8.
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*/
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#define CPFL_HAIRPIN_Q_TAIL_AUX_VALUE 8
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struct virtchnl2_p2p_rx_buf_desc {
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__le64 reserve0;
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__le64 pkt_addr; /* Packet buffer address */
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};
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struct cpfl_rxq_hairpin_info {
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bool hairpin_q; /* if rx queue is a hairpin queue */
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uint16_t peer_txp;
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uint16_t peer_txq_id;
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};
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struct cpfl_rx_queue {
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struct idpf_rx_queue base;
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struct cpfl_rxq_hairpin_info hairpin_info;
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};
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struct cpfl_txq_hairpin_info {
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bool hairpin_q; /* if tx queue is a hairpin queue */
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uint16_t peer_rxp;
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uint16_t peer_rxq_id;
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};
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struct cpfl_tx_queue {
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struct idpf_tx_queue base;
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struct cpfl_txq_hairpin_info hairpin_info;
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};
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static inline uint16_t
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cpfl_hw_qid_get(uint16_t start_qid, uint16_t offset)
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{
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return start_qid + offset;
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}
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static inline uint64_t
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cpfl_hw_qtail_get(uint64_t tail_start, uint16_t offset, uint64_t tail_spacing)
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{
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return tail_start + offset * tail_spacing;
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}
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int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
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uint16_t nb_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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int cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
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uint16_t nb_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void cpfl_stop_queues(struct rte_eth_dev *dev);
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int cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
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void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
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void cpfl_set_rx_function(struct rte_eth_dev *dev);
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void cpfl_set_tx_function(struct rte_eth_dev *dev);
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int cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
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uint16_t nb_desc, const struct rte_eth_hairpin_conf *conf);
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int cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
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uint16_t nb_desc,
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const struct rte_eth_hairpin_conf *conf);
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int cpfl_hairpin_tx_complq_config(struct cpfl_vport *cpfl_vport);
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int cpfl_hairpin_txq_config(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq);
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int cpfl_hairpin_rx_bufq_config(struct cpfl_vport *cpfl_vport);
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int cpfl_hairpin_rxq_config(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq);
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int cpfl_switch_hairpin_complq(struct cpfl_vport *cpfl_vport, bool on);
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int cpfl_switch_hairpin_bufq(struct cpfl_vport *cpfl_vport, bool on);
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int cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, uint16_t qid,
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bool rx, bool on);
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#endif /* _CPFL_RXTX_H_ */
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