mirror of https://github.com/F-Stack/f-stack.git
137 lines
2.8 KiB
C
137 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2022 Intel Corporation
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*/
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#ifndef RTE_PMD_AFU_H
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#define RTE_PMD_AFU_H
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/**
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* @file rte_pmd_afu.h
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*
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* AFU PMD specific definitions.
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*
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* @b EXPERIMENTAL: this API may change, or be removed, without prior notice
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*
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#define RTE_PMD_AFU_N3000_NLB 1
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#define RTE_PMD_AFU_N3000_DMA 2
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#define NLB_MODE_LPBK 0
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#define NLB_MODE_READ 1
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#define NLB_MODE_WRITE 2
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#define NLB_MODE_TRPUT 3
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#define NLB_VC_AUTO 0
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#define NLB_VC_VL0 1
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#define NLB_VC_VH0 2
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#define NLB_VC_VH1 3
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#define NLB_VC_RANDOM 4
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#define NLB_WRLINE_M 0
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#define NLB_WRLINE_I 1
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#define NLB_WRPUSH_I 2
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#define NLB_RDLINE_S 0
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#define NLB_RDLINE_I 1
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#define NLB_RDLINE_MIXED 2
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#define MIN_CACHE_LINES 1
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#define MAX_CACHE_LINES 1024
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#define MIN_DMA_BUF_SIZE 64
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#define MAX_DMA_BUF_SIZE (1023 * 1024)
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/**
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* NLB AFU configuration data structure.
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*/
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struct rte_pmd_afu_nlb_cfg {
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uint32_t mode;
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uint32_t begin;
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uint32_t end;
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uint32_t multi_cl;
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uint32_t cont;
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uint32_t timeout;
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uint32_t cache_policy;
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uint32_t cache_hint;
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uint32_t read_vc;
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uint32_t write_vc;
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uint32_t wrfence_vc;
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uint32_t freq_mhz;
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};
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/**
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* DMA AFU configuration data structure.
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*/
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struct rte_pmd_afu_dma_cfg {
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uint32_t index; /* index of DMA controller */
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uint32_t length; /* total length of data to DMA */
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uint32_t offset; /* address offset of target memory */
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uint32_t size; /* size of transfer buffer */
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uint32_t pattern; /* data pattern to fill in test buffer */
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uint32_t unaligned; /* use unaligned address or length in sweep test */
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uint32_t verbose; /* enable verbose error information in test */
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};
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/**
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* N3000 AFU configuration data structure.
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*/
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struct rte_pmd_afu_n3000_cfg {
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int type; /* RTE_PMD_AFU_N3000_NLB or RTE_PMD_AFU_N3000_DMA */
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union {
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struct rte_pmd_afu_nlb_cfg nlb_cfg;
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struct rte_pmd_afu_dma_cfg dma_cfg;
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};
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};
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/**
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* HE-LPBK & HE-MEM-LPBK AFU configuration data structure.
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*/
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struct rte_pmd_afu_he_lpbk_cfg {
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uint32_t mode;
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uint32_t begin;
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uint32_t end;
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uint32_t multi_cl;
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uint32_t cont;
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uint32_t timeout;
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uint32_t trput_interleave;
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uint32_t freq_mhz;
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};
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/**
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* HE-MEM-TG AFU configuration data structure.
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*/
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struct rte_pmd_afu_he_mem_tg_cfg {
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uint32_t channel_mask; /* mask of traffic generator channel */
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};
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#define NUM_RND_SEEDS 3
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/**
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* HE-HSSI AFU configuration data structure.
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*/
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struct rte_pmd_afu_he_hssi_cfg {
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uint32_t port;
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uint32_t timeout;
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uint32_t num_packets;
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uint32_t random_length;
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uint32_t packet_length;
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uint32_t random_payload;
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uint32_t rnd_seed[NUM_RND_SEEDS];
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uint64_t src_addr;
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uint64_t dest_addr;
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int he_loopback;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* RTE_PMD_AFU_H */
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