mirror of https://github.com/F-Stack/f-stack.git
557 lines
16 KiB
C
557 lines
16 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation
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*/
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#ifndef _OPAE_INTEL_MAX10_H_
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#define _OPAE_INTEL_MAX10_H_
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#include "opae_osdep.h"
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#include "opae_spi.h"
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#include "ifpga_compat.h"
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struct intel_max10_device;
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struct max10_compatible_id {
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char compatible[128];
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};
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#define MAX10_PAC "intel,max10"
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#define MAX10_PAC_N3000 "intel,max10-pac-n3000"
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#define MAX10_PAC_END "intel,end"
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/* max10 capability flags */
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#define MAX10_FLAGS_NO_I2C2 BIT(0)
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#define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1)
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#define MAX10_FLAGS_DEVICE_TABLE BIT(2)
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#define MAX10_FLAGS_SPI BIT(3)
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#define MAX10_FLGAS_NIOS_SPI BIT(4)
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#define MAX10_FLAGS_PKVL BIT(5)
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#define MAX10_FLAGS_SECURE BIT(6)
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#define MAX10_FLAGS_MAC_CACHE BIT(7)
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/** List of opae sensors */
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TAILQ_HEAD(opae_sensor_list, opae_sensor_info);
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/* Supported MAX10 BMC types */
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enum m10bmc_type {
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M10_N3000,
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M10_N6000
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};
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struct regmap_range {
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unsigned int min;
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unsigned int max;
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};
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struct m10bmc_regmap {
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int (*reg_write)(struct intel_max10_device *dev,
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unsigned int reg, unsigned int val);
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int (*reg_read)(struct intel_max10_device *dev,
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unsigned int reg, unsigned int *val);
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const struct regmap_range *range;
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int num_ranges;
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};
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struct m10bmc_csr {
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unsigned int base;
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unsigned int build_version;
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unsigned int fw_version;
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unsigned int fpga_page_info;
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unsigned int doorbell;
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unsigned int auth_result;
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};
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/**
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* struct flash_raw_blk_ops - device specific operations for flash R/W
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* @write_blk: write a block of data to flash
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* @read_blk: read a block of data from flash
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*/
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struct flash_raw_blk_ops {
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int (*write_blk)(struct intel_max10_device *dev, uint32_t addr,
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void *buf, uint32_t size);
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int (*read_blk)(struct intel_max10_device *dev, uint32_t addr,
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void *buf, uint32_t size);
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};
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/**
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* struct m10bmc_ops - device specific operations
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* @lock: prevent concurrent flash read/write
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* @mutex: prevent concurrent bmc read/write
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* @check_flash_range: validate flash address
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* @flash_read: read a block of data from flash
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* @flash_write: write a block of data to flash
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*/
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struct m10bmc_ops {
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pthread_mutex_t lock;
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pthread_mutex_t *mutex;
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int (*check_flash_range)(u32 start, u32 end);
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int (*flash_read)(struct intel_max10_device *dev, u32 addr,
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void *buf, u32 size);
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int (*flash_write)(struct intel_max10_device *dev, u32 addr,
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void *buf, u32 size);
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};
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struct intel_max10_device {
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unsigned int flags; /*max10 hardware capability*/
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struct altera_spi_device *spi_master;
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struct spi_transaction_dev *spi_tran_dev;
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struct max10_compatible_id *id; /*max10 compatible*/
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char *fdt_root;
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unsigned int base; /* max10 base address */
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u16 bus;
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struct opae_sensor_list opae_sensor_list;
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u32 staging_area_base;
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u32 staging_area_size;
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enum m10bmc_type type;
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const struct m10bmc_regmap *ops;
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const struct m10bmc_csr *csr;
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struct flash_raw_blk_ops raw_blk_ops;
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struct m10bmc_ops bmc_ops;
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u8 *mmio; /* mmio address for PMCI */
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};
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/* retimer speed */
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enum retimer_speed {
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MXD_1GB = 1,
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MXD_2_5GB = 2,
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MXD_5GB = 5,
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MXD_10GB = 10,
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MXD_25GB = 25,
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MXD_40GB = 40,
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MXD_100GB = 100,
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MXD_SPEED_UNKNOWN,
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};
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/* retimer info */
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struct opae_retimer_info {
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unsigned int nums_retimer;
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unsigned int ports_per_retimer;
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unsigned int nums_fvl;
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unsigned int ports_per_fvl;
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enum retimer_speed support_speed;
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};
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/* retimer status*/
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struct opae_retimer_status {
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enum retimer_speed speed;
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/*
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* retimer line link status bitmap:
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* bit 0: Retimer0 Port0 link status
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* bit 1: Retimer0 Port1 link status
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* bit 2: Retimer0 Port2 link status
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* bit 3: Retimer0 Port3 link status
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*
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* bit 4: Retimer1 Port0 link status
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* bit 5: Retimer1 Port1 link status
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* bit 6: Retimer1 Port2 link status
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* bit 7: Retimer1 Port3 link status
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*/
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unsigned int line_link_bitmap;
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};
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#define FLASH_BASE 0x10000000
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#define FLASH_OPTION_BITS 0x10000
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/* System Registers */
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#define MAX10_BASE_ADDR 0x300400
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#define MAX10_SEC_BASE_ADDR 0x300800
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/* Register offset of system registers */
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#define NIOS2_FW_VERSION 0x0
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#define MAX10_MACADDR1 0x10
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#define MAX10_MAC_BYTE4 GENMASK(7, 0)
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#define MAX10_MAC_BYTE3 GENMASK(15, 8)
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#define MAX10_MAC_BYTE2 GENMASK(23, 16)
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#define MAX10_MAC_BYTE1 GENMASK(31, 24)
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#define MAX10_MACADDR2 0x14
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#define MAX10_MAC_BYTE6 GENMASK(7, 0)
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#define MAX10_MAC_BYTE5 GENMASK(15, 8)
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#define MAX10_MAC_COUNT GENMASK(23, 16)
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#define RSU_REG 0x2c
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#define FPGA_RECONF_PAGE GENMASK(2, 0)
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#define FPGA_PAGE(p) ((p) & 0x1)
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#define FPGA_RP_LOAD BIT(3)
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#define NIOS2_PRERESET BIT(4)
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#define NIOS2_HANG BIT(5)
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#define RSU_ENABLE BIT(6)
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#define NIOS2_RESET BIT(7)
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#define NIOS2_I2C2_POLL_STOP BIT(13)
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#define PKVL_EEPROM_LOAD BIT(31)
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#define FPGA_RECONF_REG 0x30
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#define SFPGA_RECONF_PAGE GENMASK(22, 20)
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#define SFPGA_PAGE(p) (((p) & 0x1) << 20)
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#define SFPGA_RP_LOAD BIT(23)
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#define MAX10_TEST_REG 0x3c
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#define COUNTDOWN_START BIT(18)
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#define MAX10_BUILD_VER 0x68
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#define MAX10_VERSION_MAJOR GENMASK(23, 16)
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#define PCB_INFO GENMASK(31, 24)
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#define FPGA_PAGE_INFO 0x6c
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#define DT_AVAIL_REG 0x90
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#define DT_AVAIL BIT(0)
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#define DT_BASE_ADDR_REG 0x94
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#define MAX10_DOORBELL 0x400
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#define RSU_REQUEST BIT(0)
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#define SEC_PROGRESS GENMASK(7, 4)
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#define SEC_PROGRESS_G(v) (((v) >> 4) & 0xf)
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#define SEC_PROGRESS_IDLE 0x0
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#define SEC_PROGRESS_PREPARE 0x1
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#define SEC_PROGRESS_SLEEP 0x2
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#define SEC_PROGRESS_READY 0x3
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#define SEC_PROGRESS_AUTHENTICATING 0x4
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#define SEC_PROGRESS_COPYING 0x5
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#define SEC_PROGRESS_UPDATE_CANCEL 0x6
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#define SEC_PROGRESS_PROGRAM_KEY_HASH 0x7
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#define SEC_PROGRESS_RSU_DONE 0x8
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#define SEC_PROGRESS_PKVL_PROM_DONE 0x9
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#define HOST_STATUS GENMASK(11, 8)
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#define HOST_STATUS_S(v) (((v) << 8) & 0xf00)
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#define HOST_STATUS_IDLE 0x0
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#define HOST_STATUS_WRITE_DONE 0x1
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#define HOST_STATUS_ABORT_RSU 0x2
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#define SEC_STATUS GENMASK(23, 16)
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#define SEC_STATUS_G(v) (((v) >> 16) & 0xff)
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#define SEC_STATUS_NORMAL 0x0
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#define SEC_STATUS_TIMEOUT 0x1
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#define SEC_STATUS_AUTH_FAIL 0x2
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#define SEC_STATUS_COPY_FAIL 0x3
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#define SEC_STATUS_FATAL 0x4
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#define SEC_STATUS_PKVL_REJECT 0x5
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#define SEC_STATUS_NON_INC 0x6
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#define SEC_STATUS_ERASE_FAIL 0x7
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#define SEC_STATUS_WEAROUT 0x8
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#define SEC_STATUS_PMCI_SS_FAIL 0x9
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#define SEC_STATUS_FLASH_CMD 0xa
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#define SEC_STATUS_FACTORY_UNVERITY 0xb
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#define SEC_STATUS_FACTORY_ACTIVE 0xc
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#define SEC_STATUS_POWER_DOWN 0xd
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#define SEC_STATUS_CANCELLATION 0xe
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#define SEC_STATUS_HASH 0xf
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#define SEC_STATUS_FLASH_ACCESS 0x10
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#define SEC_STATUS_SDM_PR_CERT 0x20
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#define SEC_STATUS_SDM_PR_NIOS_BUSY 0x21
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#define SEC_STATUS_SDM_PR_TIMEOUT 0x22
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#define SEC_STATUS_SDM_PR_FAILED 0x23
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#define SEC_STATUS_SDM_PR_MISMATCH 0x24
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#define SEC_STATUS_SDM_PR_FLUSH 0x25
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#define SEC_STATUS_SDM_SR_CERT 0x30
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#define SEC_STATUS_SDM_SR_NIOS_BUSY 0x31
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#define SEC_STATUS_SDM_SR_TIMEOUT 0x32
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#define SEC_STATUS_SDM_SR_FAILED 0x33
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#define SEC_STATUS_SDM_SR_MISMATCH 0x34
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#define SEC_STATUS_SDM_SR_FLUSH 0x35
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#define SEC_STATUS_SDM_KEY_CERT 0x40
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#define SEC_STATUS_SDM_KEY_NIOS_BUSY 0x41
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#define SEC_STATUS_SDM_KEY_TIMEOUT 0x42
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#define SEC_STATUS_SDM_KEY_FAILED 0x43
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#define SEC_STATUS_SDM_KEY_MISMATCH 0x44
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#define SEC_STATUS_SDM_KEY_FLUSH 0x45
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#define SEC_STATUS_NIOS_OK 0x80
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#define SEC_STATUS_USER_OK 0x81
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#define SEC_STATUS_FACTORY_OK 0x82
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#define SEC_STATUS_USER_FAIL 0x83
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#define SEC_STATUS_FACTORY_FAIL 0x84
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#define SEC_STATUS_NIOS_FLASH_ERR 0x85
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#define SEC_STATUS_FPGA_FLASH_ERR 0x86
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#define SEC_STATUS_MAX SEC_STATUS_FPGA_FLASH_ERR
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/* Authentication status */
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#define SEC_AUTH_G(v) ((v) & 0xff)
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#define AUTH_STAT_PASS 0x0
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#define AUTH_STAT_B0_MAGIC 0x1
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#define AUTH_STAT_CONLEN 0x2
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#define AUTH_STAT_CONTYPE 0x3
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#define AUTH_STAT_B1_MAGIC 0x4
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#define AUTH_STAT_ROOT_MAGIC 0x5
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#define AUTH_STAT_CURVE_MAGIC 0x6
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#define AUTH_STAT_PERMISSION 0x7
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#define AUTH_STAT_KEY_ID 0x8
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#define AUTH_STAT_CSK_MAGIC 0x9
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#define AUTH_STAT_CSK_CURVE 0xa
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#define AUTH_STAT_CSK_PERMISSION 0xb
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#define AUTH_STAT_CSK_ID 0xc
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#define AUTH_STAT_CSK_SM 0xd
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#define AUTH_STAT_B0_E_MAGIC 0xe
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#define AUTH_STAT_B0_E_SIGN 0xf
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#define AUTH_STAT_RK_P 0x10
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#define AUTH_STAT_RE_SHA 0x11
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#define AUTH_STAT_CSK_SHA 0x12
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#define AUTH_STAT_B0_SHA 0x13
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#define AUTH_STAT_KEY_INV 0x14
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#define AUTH_STAT_KEY_CAN 0x15
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#define AUTH_STAT_UP_SHA 0x16
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#define AUTH_STAT_CAN_SHA 0x17
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#define AUTH_STAT_HASH 0x18
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#define AUTH_STAT_INV_ID 0x19
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#define AUTH_STAT_KEY_PROG 0x1a
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#define AUTH_STAT_INV_BC 0x1b
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#define AUTH_STAT_INV_SLOT 0x1c
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#define AUTH_STAT_IN_OP 0x1d
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#define AUTH_STAT_TIME_OUT 0X1e
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#define AUTH_STAT_SHA_TO 0x1f
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#define AUTH_STAT_CSK_TO 0x20
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#define AUTH_STAT_B0_TO 0x21
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#define AUTH_STAT_UP_TO 0x22
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#define AUTH_STAT_CAN_TO 0x23
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#define AUTH_STAT_HASH_TO 0x24
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#define AUTH_STAT_AUTH_IDLE 0xfe
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#define AUTH_STAT_GA_FAIL 0xff
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#define AUTH_STAT_S_ERR 0x8000
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#define AUTH_STAT_S_MN 0x8001
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#define AUTH_STAT_SH_CRC 0x8002
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#define AUTH_STAT_SD_CRC 0x8003
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#define AUTH_STAT_SD_LEN 0x8004
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#define AUTH_STAT_S_ID 0x8005
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#define AUTH_STAT_S_THR 0x8006
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#define AUTH_STAT_S_TO 0x8007
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#define AUTH_STAT_S_EN 0x8008
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#define AUTH_STAT_SF 0x8009
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#define AUTH_STAT_MAX AUTH_STAT_SF
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#define CONFIG_SEL BIT(28)
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#define CONFIG_SEL_S(v) (((v) & 0x1) << 28)
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#define REBOOT_REQ BIT(29)
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#define REBOOT_DISABLED BIT(30)
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#define MAX10_AUTH_RESULT 0x404
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/* PKVL related registers, in system register region */
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#define PKVL_POLLING_CTRL 0x80
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#define POLLING_MODE GENMASK(15, 0)
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#define PKVL_A_PRELOAD BIT(16)
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#define PKVL_A_PRELOAD_TIMEOUT BIT(17)
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#define PKVL_A_DATA_TOO_BIG BIT(18)
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#define PKVL_A_HDR_CHECKSUM BIT(20)
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#define PKVL_B_PRELOAD BIT(24)
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#define PKVL_B_PRELOAD_TIMEOUT BIT(25)
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#define PKVL_B_DATA_TOO_BIG BIT(26)
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#define PKVL_B_HDR_CHECKSUM BIT(28)
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#define PKVL_EEPROM_UPG_STATUS GENMASK(31, 16)
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#define PKVL_LINK_STATUS 0x164
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#define PKVL_A_VERSION 0x254
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#define PKVL_B_VERSION 0x258
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#define SERDES_VERSION GENMASK(15, 0)
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#define SBUS_VERSION GENMASK(31, 16)
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#define DFT_MAX_SIZE 0x7e0000
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#define MAX_STAGING_AREA_BASE 0xffffffff
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#define MAX_STAGING_AREA_SIZE 0x3800000
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#define m10bmc_base(max10) ((max10)->csr->base)
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#define doorbell_reg(max10) ((max10)->csr->doorbell)
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#define auth_result_reg(max10) ((max10)->csr->auth_result)
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int max10_sys_read(struct intel_max10_device *dev,
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unsigned int offset, unsigned int *val);
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int max10_sys_write(struct intel_max10_device *dev,
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unsigned int offset, unsigned int val);
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int max10_reg_read(struct intel_max10_device *dev,
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unsigned int offset, unsigned int *val);
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int max10_reg_write(struct intel_max10_device *dev,
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unsigned int offset, unsigned int val);
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int max10_sys_update_bits(struct intel_max10_device *dev,
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unsigned int offset, unsigned int msk, unsigned int val);
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int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned int *val);
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int max10_get_bmc_version(struct intel_max10_device *dev, unsigned int *val);
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int max10_get_fpga_load_info(struct intel_max10_device *dev, unsigned int *val);
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int intel_max10_device_init(struct intel_max10_device *dev);
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int intel_max10_device_remove(struct intel_max10_device *dev);
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#define SENSOR_REG_VALUE 0x0
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#define SENSOR_REG_HIGH_WARN 0x1
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#define SENSOR_REG_HIGH_FATAL 0x2
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#define SENSOR_REG_LOW_WARN 0x3
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#define SENSOR_REG_LOW_FATAL 0x4
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#define SENSOR_REG_HYSTERESIS 0x5
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#define SENSOR_REG_MAX 0x6
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static const char * const sensor_reg_name[] = {
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"value",
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"high_warn",
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"high_fatal",
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"low_warn",
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"low_fatal",
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"hysteresis",
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};
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struct sensor_reg {
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unsigned int regoff;
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size_t size;
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};
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struct raw_sensor_info {
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const char *name;
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const char *type;
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unsigned int id;
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unsigned int multiplier;
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struct sensor_reg regs[SENSOR_REG_MAX];
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};
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#define OPAE_SENSOR_VALID 0x1
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#define OPAE_SENSOR_HIGH_WARN_VALID 0x2
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#define OPAE_SENSOR_HIGH_FATAL_VALID 0x4
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#define OPAE_SENSOR_LOW_WARN_VALID 0x8
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#define OPAE_SENSOR_LOW_FATAL_VALID 0x10
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#define OPAE_SENSOR_HYSTERESIS_VALID 0x20
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struct opae_sensor_info {
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TAILQ_ENTRY(opae_sensor_info) node;
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const char *name;
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const char *type;
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unsigned int id;
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unsigned int high_fatal;
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unsigned int high_warn;
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unsigned int low_fatal;
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unsigned int low_warn;
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unsigned int hysteresis;
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unsigned int multiplier;
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unsigned int flags;
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unsigned int value;
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unsigned int value_reg;
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};
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#define SENSOR_INVALID 0xdeadbeef
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struct max10_sensor_raw_data {
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unsigned int reg_input;
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unsigned int reg_high_warn;
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unsigned int reg_high_fatal;
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unsigned int reg_hyst;
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unsigned int reg_low_warn;
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unsigned int multiplier;
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const char *label;
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};
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struct max10_sensor_data {
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const char *type;
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unsigned int number;
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const struct max10_sensor_raw_data *table;
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};
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enum max10_sensor_types {
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sensor_temp,
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sensor_in,
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sensor_curr,
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sensor_power,
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sensor_max,
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};
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#define SENSOR_TMP_NAME "Temperature"
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#define SENSOR_IN_NAME "Voltage"
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#define SENSOR_CURR_NAME "Current"
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#define SENSOR_POWER_NAME "Power"
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struct max10_sensor_board_data {
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const struct max10_sensor_data *tables[sensor_max];
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};
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/* indirect access for PMCI */
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#define PMCI_INDIRECT_BASE 0x400
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#define INDIRECT_CMD_OFF (PMCI_INDIRECT_BASE + 0x0)
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#define INDIRECT_CMD_RD BIT(0)
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#define INDIRECT_CMD_WR BIT(1)
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#define INDIRECT_CMD_ACK BIT(2)
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#define INDIRECT_ADDR_OFF (PMCI_INDIRECT_BASE + 0x4)
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#define INDIRECT_RD_OFF (PMCI_INDIRECT_BASE + 0x8)
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#define INDIRECT_WR_OFF (PMCI_INDIRECT_BASE + 0xc)
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#define INDIRECT_INT_US 1
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#define INDIRECT_TIMEOUT_US 10000
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#define M10BMC_PMCI_SYS_BASE 0x0
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#define M10BMC_PMCI_SYS_END 0xfff
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#define M10BMC_PMCI_BUILD_VER 0x0
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#define NIOS2_PMCI_FW_VERSION 0x4
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#define M10BMC_PMCI_PWR_STATE 0xb4
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#define PMCI_PRIMARY_IMAGE_PAGE GENMASK(10, 8)
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#define M10BMC_PMCI_DOORBELL 0x1c0
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#define PMCI_DRBL_REBOOT_DISABLED BIT(1)
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#define M10BMC_PMCI_AUTH_RESULT 0x1c4
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#define M10BMC_PMCI_MAX10_RECONF 0xfc
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#define PMCI_MAX10_REBOOT_REQ BIT(0)
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#define PMCI_MAX10_REBOOT_PAGE BIT(1)
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#define M10BMC_PMCI_FPGA_RECONF 0xb8
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#define PMCI_FPGA_RECONF_PAGE GENMASK(22, 20)
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#define PMCI_FPGA_RP_LOAD BIT(23)
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#define PMCI_FLASH_CTRL 0x40
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#define PMCI_FLASH_WR_MODE BIT(0)
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#define PMCI_FLASH_RD_MODE BIT(1)
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#define PMCI_FLASH_BUSY BIT(2)
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#define PMCI_FLASH_FIFO_SPACE GENMASK(13, 4)
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#define PMCI_FLASH_READ_COUNT GENMASK(25, 16)
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#define PMCI_FLASH_INT_US 1
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#define PMCI_FLASH_TIMEOUT_US 10000
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#define PMCI_FLASH_ADDR 0x44
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#define PMCI_FLASH_FIFO 0x800
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#define PMCI_READ_BLOCK_SIZE 0x800
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#define PMCI_FIFO_MAX_BYTES 0x800
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#define PMCI_FIFO_MAX_WORDS (PMCI_FIFO_MAX_BYTES / 4)
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#define M10BMC_PMCI_FPGA_POC 0xb0
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#define PMCI_FPGA_POC BIT(0)
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#define PMCI_NIOS_REQ_CLEAR BIT(1)
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#define PMCI_NIOS_STATUS GENMASK(5, 4)
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#define NIOS_STATUS_IDLE 0
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#define NIOS_STATUS_SUCCESS 1
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#define NIOS_STATUS_FAIL 2
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#define PMCI_USER_IMAGE_PAGE GENMASK(10, 8)
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#define POC_USER_IMAGE_1 1
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#define POC_USER_IMAGE_2 2
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#define PMCI_FACTORY_IMAGE_SEL BIT(31)
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#define M10BMC_PMCI_FPGA_CONF_STS 0xa0
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#define PMCI_FPGA_BOOT_PAGE GENMASK(2, 0)
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#define PMCI_FPGA_CONFIGURED BIT(3)
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#define M10BMC_PMCI_FLASH_CTRL 0x1d0
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#define FLASH_MUX_SELECTION GENMASK(2, 0)
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#define FLASH_MUX_IDLE 0
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#define FLASH_MUX_NIOS 1
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#define FLASH_MUX_HOST 2
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#define FLASH_MUX_PFL 4
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#define get_flash_mux(mux) GET_FIELD(FLASH_MUX_SELECTION, mux)
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#define FLASH_NIOS_REQUEST BIT(4)
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#define FLASH_HOST_REQUEST BIT(5)
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#define M10BMC_PMCI_SDM_CTRL_STS 0x230
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#define PMCI_SDM_IMG_REQ BIT(0)
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#define PMCI_SDM_STAT GENMASK(23, 16)
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#define SDM_STAT_DONE 0x0
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#define SDM_STAT_PROV 0x1
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#define SDM_STAT_BUSY 0x2
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#define SDM_STAT_INV 0x3
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#define SDM_STAT_FAIL 0x4
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#define SDM_STAT_BMC_BUSY 0x5
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#define SDM_STAT_TO 0x6
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#define SDM_STAT_DB 0x7
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#define SDM_STAT_CON_R 0x8
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#define SDM_STAT_CON_E 0x9
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#define SDM_STAT_WAIT 0xa
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#define SDM_STAT_RTO 0xb
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#define SDM_STAT_SB 0xc
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#define SDM_STAT_RE 0xd
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#define SDM_STAT_PDD 0xe
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#define SDM_STAT_ISC 0xf
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#define SDM_STAT_SIC 0x10
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#define SDM_STAT_NO_PROV 0x11
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#define SDM_STAT_CS_MIS 0x12
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#define SDM_STAT_PR_MIS 0x13
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#define SDM_STAT_MAX SDM_STAT_PR_MIS
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#define PMCI_FLASH_START 0x10000
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#define PMCI_FLASH_END 0xC7FFFFF
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int opae_read_flash(struct intel_max10_device *dev, u32 addr,
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u32 size, void *buf);
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#endif
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