mirror of https://github.com/F-Stack/f-stack.git
340 lines
7.3 KiB
C
340 lines
7.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#ifndef AFU_PMD_N3000_H
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#define AFU_PMD_N3000_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "afu_pmd_core.h"
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#include "rte_pmd_afu.h"
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#define N3000_AFU_UUID_L 0xc000c9660d824272
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#define N3000_AFU_UUID_H 0x9aeffe5f84570612
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#define N3000_NLB0_UUID_L 0xf89e433683f9040b
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#define N3000_NLB0_UUID_H 0xd8424dc4a4a3c413
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#define N3000_DMA_UUID_L 0xa9149a35bace01ea
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#define N3000_DMA_UUID_H 0xef82def7f6ec40fc
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#define NUM_N3000_DMA 4
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#define MAX_MSIX_VEC 7
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/* N3000 DFL definition */
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#define DFH_UUID_L_OFFSET 8
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#define DFH_UUID_H_OFFSET 16
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#define DFH_TYPE(hdr) (((hdr) >> 60) & 0xf)
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#define DFH_TYPE_AFU 1
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#define DFH_TYPE_BBB 2
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#define DFH_TYPE_PRIVATE 3
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#define DFH_EOL(hdr) (((hdr) >> 40) & 0x1)
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#define DFH_NEXT_OFFSET(hdr) (((hdr) >> 16) & 0xffffff)
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#define DFH_FEATURE_ID(hdr) ((hdr) & 0xfff)
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#define PORT_ATTR_REG(n) (((n) << 3) + 0x38)
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#define PORT_IMPLEMENTED(attr) (((attr) >> 60) & 0x1)
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#define PORT_BAR(attr) (((attr) >> 32) & 0x7)
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#define PORT_OFFSET(attr) ((attr) & 0xffffff)
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#define PORT_FEATURE_UINT_ID 0x12
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#define PORT_UINT_CAP_REG 0x8
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#define PORT_VEC_START(cap) (((cap) >> 12) & 0xfff)
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#define PORT_VEC_COUNT(cap) ((cap) >> 12 & 0xfff)
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#define PORT_CTRL_REG 0x38
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#define PORT_SOFT_RESET (0x1 << 0)
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/* NLB registers definition */
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#define CSR_SCRATCHPAD0 0x100
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#define CSR_SCRATCHPAD1 0x108
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#define CSR_AFU_DSM_BASEL 0x110
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#define CSR_AFU_DSM_BASEH 0x114
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#define CSR_SRC_ADDR 0x120
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#define CSR_DST_ADDR 0x128
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#define CSR_NUM_LINES 0x130
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#define CSR_CTL 0x138
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#define CSR_CFG 0x140
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#define CSR_INACT_THRESH 0x148
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#define CSR_INTERRUPT0 0x150
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#define CSR_SWTEST_MSG 0x158
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#define CSR_STATUS0 0x160
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#define CSR_STATUS1 0x168
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#define CSR_ERROR 0x170
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#define CSR_STRIDE 0x178
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#define CSR_HE_INFO0 0x180
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#define DSM_SIZE 0x200000
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#define DSM_STATUS 0x40
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#define DSM_POLL_INTERVAL 5 /* ms */
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#define DSM_TIMEOUT 1000 /* ms */
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#define NLB_BUF_SIZE 0x400000
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#define TEST_MEM_ALIGN 1024
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struct nlb_csr_ctl {
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union {
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uint32_t csr;
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struct {
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uint32_t reset:1;
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uint32_t start:1;
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uint32_t force_completion:1;
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uint32_t reserved:29;
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};
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};
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};
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struct nlb_csr_cfg {
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union {
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uint32_t csr;
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struct {
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uint32_t wrthru_en:1;
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uint32_t cont:1;
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uint32_t mode:3;
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uint32_t multicl_len:2;
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uint32_t rsvd1:1;
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uint32_t delay_en:1;
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uint32_t rdsel:2;
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uint32_t rsvd2:1;
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uint32_t chsel:3;
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uint32_t rsvd3:1;
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uint32_t wrpush_i:1;
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uint32_t wr_chsel:3;
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uint32_t rsvd4:3;
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uint32_t test_cfg:5;
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uint32_t interrupt_on_error:1;
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uint32_t interrupt_testmode:1;
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uint32_t wrfence_chsel:2;
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};
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};
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};
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struct nlb_status0 {
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union {
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uint64_t csr;
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struct {
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uint32_t num_writes;
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uint32_t num_reads;
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};
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};
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};
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struct nlb_status1 {
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union {
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uint64_t csr;
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struct {
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uint32_t num_pend_writes;
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uint32_t num_pend_reads;
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};
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};
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};
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struct nlb_dsm_status {
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uint32_t test_complete;
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uint32_t test_error;
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uint64_t num_clocks;
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uint32_t num_reads;
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uint32_t num_writes;
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uint32_t start_overhead;
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uint32_t end_overhead;
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};
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/* DMA registers definition */
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#define DMA_CSR 0x40
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#define DMA_DESC 0x60
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#define DMA_ASE_CTRL 0x200
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#define DMA_ASE_DATA 0x1000
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#define DMA_ASE_WINDOW 4096
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#define DMA_ASE_WINDOW_MASK ((uint64_t)(DMA_ASE_WINDOW - 1))
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#define INVALID_ASE_PAGE 0xffffffffffffffffULL
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#define DMA_WF_MAGIC 0x5772745F53796E63ULL
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#define DMA_WF_MAGIC_ROM 0x1000000000000
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#define DMA_HOST_ADDR(addr) ((addr) | 0x2000000000000)
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#define DMA_WF_HOST_ADDR(addr) ((addr) | 0x3000000000000)
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#define NUM_DMA_BUF 8
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#define HALF_DMA_BUF (NUM_DMA_BUF / 2)
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#define DMA_MASK_32_BIT 0xFFFFFFFF
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#define DMA_CSR_BUSY 0x1
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#define DMA_DESC_BUFFER_EMPTY 0x2
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#define DMA_DESC_BUFFER_FULL 0x4
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#define DWORD_BYTES 4
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#define IS_ALIGNED_DWORD(addr) (((addr) % DWORD_BYTES) == 0)
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#define QWORD_BYTES 8
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#define IS_ALIGNED_QWORD(addr) (((addr) % QWORD_BYTES) == 0)
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#define DMA_ALIGN_BYTES 64
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#define IS_DMA_ALIGNED(addr) (((addr) % DMA_ALIGN_BYTES) == 0)
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#define CCIP_ALIGN_BYTES (DMA_ALIGN_BYTES << 2)
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#define DMA_TIMEOUT_MSEC 5000
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#define MAGIC_BUF_SIZE 64
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#define ERR_CHECK_LIMIT 64
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#ifndef MIN
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#endif
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#ifndef ARRAY_SIZE
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#endif
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typedef enum {
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HOST_TO_FPGA = 0,
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FPGA_TO_HOST,
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FPGA_TO_FPGA,
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FPGA_MAX_TRANSFER_TYPE,
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} fpga_dma_type;
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typedef union {
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uint32_t csr;
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struct {
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uint32_t tx_channel:8;
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uint32_t generate_sop:1;
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uint32_t generate_eop:1;
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uint32_t park_reads:1;
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uint32_t park_writes:1;
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uint32_t end_on_eop:1;
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uint32_t reserved_1:1;
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uint32_t transfer_irq_en:1;
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uint32_t early_term_irq_en:1;
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uint32_t trans_error_irq_en:8;
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uint32_t early_done_en:1;
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uint32_t reserved_2:6;
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uint32_t go:1;
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};
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} msgdma_desc_ctrl;
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typedef struct __rte_packed {
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uint32_t rd_address;
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uint32_t wr_address;
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uint32_t len;
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uint16_t seq_num;
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uint8_t rd_burst_count;
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uint8_t wr_burst_count;
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uint16_t rd_stride;
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uint16_t wr_stride;
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uint32_t rd_address_ext;
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uint32_t wr_address_ext;
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msgdma_desc_ctrl control;
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} msgdma_ext_desc;
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typedef union {
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uint32_t csr;
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struct {
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uint32_t busy:1;
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uint32_t desc_buf_empty:1;
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uint32_t desc_buf_full:1;
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uint32_t rsp_buf_empty:1;
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uint32_t rsp_buf_full:1;
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uint32_t stopped:1;
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uint32_t resetting:1;
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uint32_t stopped_on_error:1;
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uint32_t stopped_on_early_term:1;
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uint32_t irq:1;
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uint32_t reserved:22;
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};
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} msgdma_status;
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typedef union {
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uint32_t csr;
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struct {
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uint32_t stop_dispatcher:1;
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uint32_t reset_dispatcher:1;
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uint32_t stop_on_error:1;
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uint32_t stopped_on_early_term:1;
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uint32_t global_intr_en_mask:1;
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uint32_t stop_descriptors:1;
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uint32_t reserved:22;
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};
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} msgdma_ctrl;
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typedef union {
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uint32_t csr;
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struct {
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uint32_t rd_fill_level:16;
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uint32_t wr_fill_level:16;
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};
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} msgdma_fill_level;
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typedef union {
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uint32_t csr;
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struct {
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uint32_t rsp_fill_level:16;
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uint32_t reserved:16;
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};
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} msgdma_rsp_level;
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typedef union {
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uint32_t csr;
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struct {
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uint32_t rd_seq_num:16;
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uint32_t wr_seq_num:16;
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};
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} msgdma_seq_num;
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typedef struct __rte_packed {
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msgdma_status status;
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msgdma_ctrl ctrl;
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msgdma_fill_level fill_level;
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msgdma_rsp_level rsp;
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msgdma_seq_num seq_num;
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} msgdma_csr;
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#define CSR_STATUS(csr) (&(((msgdma_csr *)(csr))->status))
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#define CSR_CONTROL(csr) (&(((msgdma_csr *)(csr))->ctrl))
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struct nlb_afu_ctx {
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uint8_t *addr;
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uint8_t *dsm_ptr;
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uint64_t dsm_iova;
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uint8_t *src_ptr;
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uint64_t src_iova;
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uint8_t *dest_ptr;
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uint64_t dest_iova;
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struct nlb_dsm_status *status_ptr;
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};
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struct dma_afu_ctx {
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int index;
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uint8_t *addr;
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uint8_t *csr_addr;
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uint8_t *desc_addr;
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uint8_t *ase_ctrl_addr;
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uint8_t *ase_data_addr;
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uint64_t mem_size;
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uint64_t cur_ase_page;
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int event_fd;
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int verbose;
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int pattern;
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void *data_buf;
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void *ref_buf;
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msgdma_ext_desc *desc_buf;
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uint64_t *magic_buf;
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uint64_t magic_iova;
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uint32_t dma_buf_size;
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uint64_t *dma_buf[NUM_DMA_BUF];
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uint64_t dma_iova[NUM_DMA_BUF];
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};
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struct n3000_afu_priv {
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struct rte_pmd_afu_nlb_cfg nlb_cfg;
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struct rte_pmd_afu_dma_cfg dma_cfg;
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struct nlb_afu_ctx nlb_ctx;
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struct dma_afu_ctx dma_ctx[NUM_N3000_DMA];
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int num_dma;
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int cfg_type;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* AFU_PMD_N3000_H */
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