mirror of https://github.com/F-Stack/f-stack.git
162 lines
5.8 KiB
C
162 lines
5.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2022 Marvell.
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*/
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#ifndef _CNXK_EP_VF_H_
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#define _CNXK_EP_VF_H_
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#include <rte_io.h>
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#include "otx_ep_common.h"
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#define CNXK_CONFIG_XPANSION_BAR 0x38
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#define CNXK_CONFIG_PCIE_CAP 0x70
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#define CNXK_CONFIG_PCIE_DEVCAP 0x74
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#define CNXK_CONFIG_PCIE_DEVCTL 0x78
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#define CNXK_CONFIG_PCIE_LINKCAP 0x7C
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#define CNXK_CONFIG_PCIE_LINKCTL 0x80
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#define CNXK_CONFIG_PCIE_SLOTCAP 0x84
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#define CNXK_CONFIG_PCIE_SLOTCTL 0x88
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#define CNXK_CONFIG_PCIE_FLTMSK 0x720
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#define CNXK_EP_RING_OFFSET (0x1ULL << 17)
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#define CNXK_EP_R_IN_CONTROL_START 0x10000
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#define CNXK_EP_R_IN_ENABLE_START 0x10010
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#define CNXK_EP_R_IN_INSTR_BADDR_START 0x10020
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#define CNXK_EP_R_IN_INSTR_RSIZE_START 0x10030
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#define CNXK_EP_R_IN_INSTR_DBELL_START 0x10040
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#define CNXK_EP_R_IN_CNTS_START 0x10050
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#define CNXK_EP_R_IN_INT_LEVELS_START 0x10060
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#define CNXK_EP_R_IN_PKT_CNT_START 0x10080
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#define CNXK_EP_R_IN_BYTE_CNT_START 0x10090
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#define CNXK_EP_R_IN_CONTROL(ring) \
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(CNXK_EP_R_IN_CONTROL_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_ENABLE(ring) \
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(CNXK_EP_R_IN_ENABLE_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_INSTR_BADDR(ring) \
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(CNXK_EP_R_IN_INSTR_BADDR_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_INSTR_RSIZE(ring) \
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(CNXK_EP_R_IN_INSTR_RSIZE_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_INSTR_DBELL(ring) \
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(CNXK_EP_R_IN_INSTR_DBELL_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_CNTS(ring) \
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(CNXK_EP_R_IN_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_INT_LEVELS(ring) \
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(CNXK_EP_R_IN_INT_LEVELS_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_PKT_CNT(ring) \
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(CNXK_EP_R_IN_PKT_CNT_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_IN_BYTE_CNT(ring) \
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(CNXK_EP_R_IN_BYTE_CNT_START + ((ring) * CNXK_EP_RING_OFFSET))
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/** Rings per Virtual Function **/
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#define CNXK_EP_R_IN_CTL_RPVF_MASK (0xF)
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#define CNXK_EP_R_IN_CTL_RPVF_POS (48)
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/* Number of instructions to be read in one MAC read request.
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* setting to Max value(4)
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*/
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#define CNXK_EP_R_IN_CTL_IDLE (0x1ULL << 28)
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#define CNXK_EP_R_IN_CTL_RDSIZE (0x3ULL << 25)
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#define CNXK_EP_R_IN_CTL_IS_64B (0x1ULL << 24)
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#define CNXK_EP_R_IN_CTL_D_NSR (0x1ULL << 8)
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#define CNXK_EP_R_IN_CTL_D_ROR (0x1ULL << 5)
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#define CNXK_EP_R_IN_CTL_NSR (0x1ULL << 3)
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#define CNXK_EP_R_IN_CTL_ROR (0x1ULL << 0)
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#define CNXK_EP_R_IN_CTL_ESR (0x1ull << 1)
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#define CNXK_EP_R_IN_CTL_MASK \
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(CNXK_EP_R_IN_CTL_RDSIZE \
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| CNXK_EP_R_IN_CTL_IS_64B)
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#define CNXK_EP_R_OUT_CNTS_START 0x10100
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#define CNXK_EP_R_OUT_INT_LEVELS_START 0x10110
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#define CNXK_EP_R_OUT_SLIST_BADDR_START 0x10120
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#define CNXK_EP_R_OUT_SLIST_RSIZE_START 0x10130
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#define CNXK_EP_R_OUT_SLIST_DBELL_START 0x10140
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#define CNXK_EP_R_OUT_CONTROL_START 0x10150
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/* WMARK need to be set; New in CN10K */
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#define CNXK_EP_R_OUT_WMARK_START 0x10160
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#define CNXK_EP_R_OUT_ENABLE_START 0x10170
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#define CNXK_EP_R_OUT_PKT_CNT_START 0x10180
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#define CNXK_EP_R_OUT_BYTE_CNT_START 0x10190
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#define CNXK_EP_R_OUT_CNTS(ring) \
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(CNXK_EP_R_OUT_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_INT_LEVELS(ring) \
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(CNXK_EP_R_OUT_INT_LEVELS_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_SLIST_BADDR(ring) \
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(CNXK_EP_R_OUT_SLIST_BADDR_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_SLIST_RSIZE(ring) \
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(CNXK_EP_R_OUT_SLIST_RSIZE_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_SLIST_DBELL(ring) \
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(CNXK_EP_R_OUT_SLIST_DBELL_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_CONTROL(ring) \
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(CNXK_EP_R_OUT_CONTROL_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_ENABLE(ring) \
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(CNXK_EP_R_OUT_ENABLE_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_WMARK(ring) \
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(CNXK_EP_R_OUT_WMARK_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_PKT_CNT(ring) \
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(CNXK_EP_R_OUT_PKT_CNT_START + ((ring) * CNXK_EP_RING_OFFSET))
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#define CNXK_EP_R_OUT_BYTE_CNT(ring) \
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(CNXK_EP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_EP_RING_OFFSET))
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/*------------------ R_OUT Masks ----------------*/
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#define CNXK_EP_R_OUT_INT_LEVELS_BMODE (1ULL << 63)
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#define CNXK_EP_R_OUT_INT_LEVELS_TIMET (32)
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#define CNXK_EP_R_OUT_CTL_IDLE (1ULL << 40)
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#define CNXK_EP_R_OUT_CTL_ES_I (1ull << 34)
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#define CNXK_EP_R_OUT_CTL_NSR_I (1ULL << 33)
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#define CNXK_EP_R_OUT_CTL_ROR_I (1ULL << 32)
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#define CNXK_EP_R_OUT_CTL_ES_D (1ull << 30)
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#define CNXK_EP_R_OUT_CTL_NSR_D (1ULL << 29)
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#define CNXK_EP_R_OUT_CTL_ROR_D (1ULL << 28)
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#define CNXK_EP_R_OUT_CTL_ES_P (1ull << 26)
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#define CNXK_EP_R_OUT_CTL_NSR_P (1ULL << 25)
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#define CNXK_EP_R_OUT_CTL_ROR_P (1ULL << 24)
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#define CNXK_EP_R_OUT_CTL_IMODE (1ULL << 23)
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#define PCI_DEVID_CNXK_EP_NET_VF 0xB903
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int
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cnxk_ep_vf_setup_device(struct otx_ep_device *sdpvf);
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struct cnxk_ep_instr_64B {
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/* Pointer where the input data is available. */
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uint64_t dptr;
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/* OTX_EP Instruction Header. */
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union otx_ep_instr_ih ih;
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/** Pointer where the response for a RAW mode packet
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* will be written by OCTEON TX.
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*/
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uint64_t rptr;
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/* Input Request Header. */
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union otx_ep_instr_irh irh;
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/* Additional headers available in a 64-byte instruction. */
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uint64_t exhdr[4];
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};
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#endif /*_CNXK_EP_VF_H_ */
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