mirror of https://github.com/F-Stack/f-stack.git
377 lines
11 KiB
C
377 lines
11 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
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* driver. They are only included via qbman_private.h, which is itself a
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* platform-independent file and is included by all the other driver source.
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*
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* qbman_sys_decl.h is included prior to all other declarations and logic, and
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* it exists to provide compatibility with any linux interfaces our
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* single-source driver code is dependent on (eg. kmalloc). Ie. this file
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* provides linux compatibility.
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*
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* This qbman_sys.h header, on the other hand, is included *after* any common
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* and platform-neutral declarations and logic in qbman_private.h, and exists to
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* implement any platform-specific logic of the qbman driver itself. Ie. it is
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* *not* to provide linux compatibility.
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*/
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#include "qbman_sys_decl.h"
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/* Debugging assists */
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static inline void __hexdump(unsigned long start, unsigned long end,
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unsigned long p, size_t sz, const unsigned char *c)
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{
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while (start < end) {
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unsigned int pos = 0;
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char buf[64];
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int nl = 0;
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pos += sprintf(buf + pos, "%08lx: ", start);
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do {
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if ((start < p) || (start >= (p + sz)))
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pos += sprintf(buf + pos, "..");
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else
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pos += sprintf(buf + pos, "%02x", *(c++));
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if (!(++start & 15)) {
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buf[pos++] = '\n';
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nl = 1;
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} else {
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nl = 0;
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if (!(start & 1))
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buf[pos++] = ' ';
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if (!(start & 3))
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buf[pos++] = ' ';
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}
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} while (start & 15);
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if (!nl)
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buf[pos++] = '\n';
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buf[pos] = '\0';
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pr_info("%s", buf);
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}
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}
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static inline void hexdump(const void *ptr, size_t sz)
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{
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unsigned long p = (unsigned long)ptr;
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unsigned long start = p & ~15;
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unsigned long end = (p + sz + 15) & ~15;
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const unsigned char *c = ptr;
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__hexdump(start, end, p, sz, c);
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}
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/* Currently, the CENA support code expects each 32-bit word to be written in
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* host order, and these are converted to hardware (little-endian) order on
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* command submission. However, 64-bit quantities are must be written (and read)
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* as two 32-bit words with the least-significant word first, irrespective of
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* host endianness.
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*/
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static inline void u64_to_le32_copy(void *d, const uint64_t *s,
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unsigned int cnt)
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{
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uint32_t *dd = d;
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const uint32_t *ss = (const uint32_t *)s;
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while (cnt--) {
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/* TBD: the toolchain was choking on the use of 64-bit types up
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* until recently so this works entirely with 32-bit variables.
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* When 64-bit types become usable again, investigate better
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* ways of doing this.
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*/
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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*(dd++) = ss[1];
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*(dd++) = ss[0];
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ss += 2;
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#else
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*(dd++) = *(ss++);
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*(dd++) = *(ss++);
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#endif
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}
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}
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static inline void u64_from_le32_copy(uint64_t *d, const void *s,
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unsigned int cnt)
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{
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const uint32_t *ss = s;
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uint32_t *dd = (uint32_t *)d;
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while (cnt--) {
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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dd[1] = *(ss++);
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dd[0] = *(ss++);
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dd += 2;
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#else
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*(dd++) = *(ss++);
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*(dd++) = *(ss++);
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#endif
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}
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}
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/******************/
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/* Portal access */
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/******************/
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struct qbman_swp_sys {
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/* On GPP, the sys support for qbman_swp is here. The CENA region isi
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* not an mmap() of the real portal registers, but an allocated
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* place-holder, because the actual writes/reads to/from the portal are
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* marshalled from these allocated areas using QBMan's "MC access
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* registers". CINH accesses are atomic so there's no need for a
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* place-holder.
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*/
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uint8_t *cena;
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uint8_t __iomem *addr_cena;
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uint8_t __iomem *addr_cinh;
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uint32_t idx;
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enum qbman_eqcr_mode eqcr_mode;
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};
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/* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
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* C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
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* SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
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* P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
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* T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
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* E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
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*/
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static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
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uint32_t val)
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{
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__raw_writel(val, s->addr_cinh + offset);
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#ifdef QBMAN_CINH_TRACE
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pr_info("qbman_cinh_write(%p:%d:0x%03x) 0x%08x\n",
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s->addr_cinh, s->idx, offset, val);
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#endif
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}
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static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
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{
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uint32_t reg = __raw_readl(s->addr_cinh + offset);
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#ifdef QBMAN_CINH_TRACE
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pr_info("qbman_cinh_read(%p:%d:0x%03x) 0x%08x\n",
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s->addr_cinh, s->idx, offset, reg);
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#endif
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return reg;
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}
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static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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void *shadow = s->cena + offset;
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_write_start(%p:%d:0x%03x) %p\n",
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s->addr_cena, s->idx, offset, shadow);
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#endif
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QBMAN_BUG_ON(offset & 63);
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dcbz(shadow);
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return shadow;
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}
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static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n",
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s->addr_cena, s->idx, offset);
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#endif
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QBMAN_BUG_ON(offset & 63);
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return (s->addr_cena + offset);
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}
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static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
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uint32_t offset, void *cmd)
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{
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const uint32_t *shadow = cmd;
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int loop;
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_write_complete(%p:%d:0x%03x) %p\n",
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s->addr_cena, s->idx, offset, shadow);
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hexdump(cmd, 64);
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#endif
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for (loop = 15; loop >= 1; loop--)
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__raw_writel(shadow[loop], s->addr_cena +
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offset + loop * 4);
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lwsync();
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__raw_writel(shadow[0], s->addr_cena + offset);
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dcbf(s->addr_cena + offset);
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}
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static inline void qbman_cena_write_complete_wo_shadow(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_write_complete(%p:%d:0x%03x)\n",
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s->addr_cena, s->idx, offset);
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#endif
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dcbf(s->addr_cena + offset);
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}
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static inline uint32_t qbman_cena_read_reg(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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return __raw_readl(s->addr_cena + offset);
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}
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static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
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{
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uint32_t *shadow = (uint32_t *)(s->cena + offset);
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unsigned int loop;
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n",
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s->addr_cena, s->idx, offset, shadow);
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#endif
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for (loop = 0; loop < 16; loop++)
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shadow[loop] = __raw_readl(s->addr_cena + offset
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+ loop * 4);
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#ifdef QBMAN_CENA_TRACE
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hexdump(shadow, 64);
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#endif
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return shadow;
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}
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static inline void *qbman_cena_read_wo_shadow(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_read(%p:%d:0x%03x)\n",
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s->addr_cena, s->idx, offset);
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#endif
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return s->addr_cena + offset;
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}
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static inline void qbman_cena_invalidate(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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dccivac(s->addr_cena + offset);
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}
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static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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dccivac(s->addr_cena + offset);
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prefetch_for_load(s->addr_cena + offset);
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}
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static inline void qbman_cena_prefetch(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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prefetch_for_load(s->addr_cena + offset);
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}
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/******************/
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/* Portal support */
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/******************/
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/* The SWP_CFG portal register is special, in that it is used by the
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* platform-specific code rather than the platform-independent code in
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* qbman_portal.c. So use of it is declared locally here.
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*/
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#define QBMAN_CINH_SWP_CFG 0xd00
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#define QBMAN_CINH_SWP_CFG 0xd00
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#define SWP_CFG_DQRR_MF_SHIFT 20
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#define SWP_CFG_EST_SHIFT 16
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#define SWP_CFG_WN_SHIFT 14
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#define SWP_CFG_RPM_SHIFT 12
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#define SWP_CFG_DCM_SHIFT 10
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#define SWP_CFG_EPM_SHIFT 8
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#define SWP_CFG_SD_SHIFT 5
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#define SWP_CFG_SP_SHIFT 4
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#define SWP_CFG_SE_SHIFT 3
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#define SWP_CFG_DP_SHIFT 2
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#define SWP_CFG_DE_SHIFT 1
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#define SWP_CFG_EP_SHIFT 0
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static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
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uint8_t est, uint8_t rpm, uint8_t dcm,
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uint8_t epm, int sd, int sp, int se,
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int dp, int de, int ep)
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{
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uint32_t reg;
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reg = (max_fill << SWP_CFG_DQRR_MF_SHIFT |
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est << SWP_CFG_EST_SHIFT |
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wn << SWP_CFG_WN_SHIFT |
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rpm << SWP_CFG_RPM_SHIFT |
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dcm << SWP_CFG_DCM_SHIFT |
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epm << SWP_CFG_EPM_SHIFT |
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sd << SWP_CFG_SD_SHIFT |
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sp << SWP_CFG_SP_SHIFT |
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se << SWP_CFG_SE_SHIFT |
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dp << SWP_CFG_DP_SHIFT |
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de << SWP_CFG_DE_SHIFT |
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ep << SWP_CFG_EP_SHIFT);
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return reg;
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}
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static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
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const struct qbman_swp_desc *d,
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uint8_t dqrr_size)
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{
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uint32_t reg;
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s->addr_cena = d->cena_bar;
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s->addr_cinh = d->cinh_bar;
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s->idx = (uint32_t)d->idx;
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s->cena = malloc(4096);
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if (!s->cena) {
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pr_err("Could not allocate page for cena shadow\n");
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return -1;
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}
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s->eqcr_mode = d->eqcr_mode;
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QBMAN_BUG_ON(d->idx < 0);
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#ifdef QBMAN_CHECKING
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/* We should never be asked to initialise for a portal that isn't in
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* the power-on state. (Ie. don't forget to reset portals when they are
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* decommissioned!)
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*/
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reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
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QBMAN_BUG_ON(reg);
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#endif
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if (s->eqcr_mode == qman_eqcr_vb_array)
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reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1,
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1, 1);
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else
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reg = qbman_set_swp_cfg(dqrr_size, 0, 2, 3, 2, 2, 1, 1, 1, 1,
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1, 1);
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qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
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reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
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if (!reg) {
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pr_err("The portal %d is not enabled!\n", s->idx);
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free(s->cena);
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return -1;
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}
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return 0;
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}
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static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
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{
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free(s->cena);
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}
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