mirror of https://github.com/F-Stack/f-stack.git
91 lines
3.6 KiB
C
91 lines
3.6 KiB
C
/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**************************************************************************//**
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@File core_ext.h
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@Description Generic interface to basic core operations.
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The system integrator must ensure that this interface is
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mapped to a specific core implementation, by including the
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appropriate header file.
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*//***************************************************************************/
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#ifndef __CORE_EXT_H
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#define __CORE_EXT_H
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#ifdef CONFIG_FMAN_ARM
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#include "arm_ext.h"
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#include <linux/smp.h>
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#else
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#ifdef NCSW_PPC_CORE
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#include "ppc_ext.h"
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#elif defined(NCSW_VXWORKS)
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#include "core_vxw_ext.h"
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#else
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#error "Core is not defined!"
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#endif /* NCSW_CORE */
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#if (!defined(CORE_IS_LITTLE_ENDIAN) && !defined(CORE_IS_BIG_ENDIAN))
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#error "Must define core as little-endian or big-endian!"
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#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */
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#ifndef CORE_CACHELINE_SIZE
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#error "Must define the core cache-line size!"
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#endif /* !CORE_CACHELINE_SIZE */
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#endif /* CONFIG_FMAN_ARM */
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/**************************************************************************//**
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@Function CORE_GetId
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@Description Returns the core ID in the system.
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@Return Core ID.
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*//***************************************************************************/
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uint32_t CORE_GetId(void);
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/**************************************************************************//**
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@Function CORE_MemoryBarrier
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@Description This routine will cause the core to stop executing any commands
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until all previous memory read/write commands are completely out
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of the core's pipeline.
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@Return None.
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*//***************************************************************************/
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void CORE_MemoryBarrier(void);
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#define fsl_mem_core_barrier() CORE_MemoryBarrier()
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#endif /* __CORE_EXT_H */
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