mirror of https://github.com/F-Stack/f-stack.git
Sync DPDK's modifies.
1. igb_uio.
2. mlx5 drivers.
3. i40e drivers.
4. Freebsd-13.1.
This commit is contained in:
fengbojiang
parent
bfa9c1237f
commit
c408ecc698
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@ -1514,7 +1514,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
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}
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/* Firmware of SFP x722 does not support 802.1ad frames ability */
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if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
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hw->device_id == I40E_DEV_ID_SFP_I_X722)
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hw->device_id == I40E_DEV_ID_SFP_I_X722 ||
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hw->device_id == I40E_DEV_ID_10G_BASE_T_X722)
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hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
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PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
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@ -23,6 +23,7 @@
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#include <stdalign.h>
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#include <sys/un.h>
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#include <time.h>
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#include <dlfcn.h>
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#include <ethdev_driver.h>
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#include <bus_pci_driver.h>
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@ -1045,6 +1046,7 @@ mlx5_sysfs_check_switch_info(bool device_dir,
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int (*real_if_indextoname)(unsigned int, char *);
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int
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mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info)
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{
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@ -1065,7 +1067,16 @@ mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info)
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char c;
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ssize_t line_size;
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if (!if_indextoname(ifindex, ifname)) {
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// for ff tools
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if (!real_if_indextoname) {
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real_if_indextoname = dlsym(RTLD_NEXT, "if_indextoname");
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if (!real_if_indextoname) {
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rte_errno = errno;
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return -rte_errno;
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}
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}
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if (!real_if_indextoname(ifindex, ifname)) {
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rte_errno = errno;
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return -rte_errno;
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}
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@ -0,0 +1,2 @@
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ccflags-y := $(MODULE_CFLAGS)
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obj-m := igb_uio.o
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@ -0,0 +1,7 @@
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KSRC ?= /lib/modules/$(shell uname -r)/build
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all:
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make -C $(KSRC)/ M=$(CURDIR)
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%:
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make -C $(KSRC)/ M=$(CURDIR) $@
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@ -0,0 +1,168 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Minimal wrappers to allow compiling igb_uio on older kernels.
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*/
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#ifndef RHEL_RELEASE_VERSION
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#define RHEL_RELEASE_VERSION(a, b) (((a) << 8) + (b))
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
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#define pci_cfg_access_lock pci_block_user_cfg_access
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#define pci_cfg_access_unlock pci_unblock_user_cfg_access
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
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#define HAVE_PTE_MASK_PAGE_IOMAP
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#endif
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#ifndef PCI_MSIX_ENTRY_SIZE
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
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#endif
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/*
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* for kernels < 2.6.38 and backported patch that moves MSI-X entry definition
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* to pci_regs.h Those kernels has PCI_MSIX_ENTRY_SIZE defined but not
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* PCI_MSIX_ENTRY_CTRL_MASKBIT
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*/
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#ifndef PCI_MSIX_ENTRY_CTRL_MASKBIT
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34) && \
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(!(defined(RHEL_RELEASE_CODE) && \
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RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 9)))
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static int pci_num_vf(struct pci_dev *dev)
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{
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struct iov {
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int pos;
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int nres;
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u32 cap;
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u16 ctrl;
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u16 total;
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u16 initial;
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u16 nr_virtfn;
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} *iov = (struct iov *)dev->sriov;
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if (!dev->is_physfn)
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return 0;
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return iov->nr_virtfn;
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}
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#endif /* < 2.6.34 */
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && \
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(!(defined(RHEL_RELEASE_CODE) && \
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RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))
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#define kstrtoul strict_strtoul
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#endif /* < 2.6.39 */
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0) && \
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(!(defined(RHEL_RELEASE_CODE) && \
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RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)))
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/* Check if INTX works to control irq's.
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* Set's INTX_DISABLE flag and reads it back
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*/
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static bool pci_intx_mask_supported(struct pci_dev *pdev)
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{
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bool mask_supported = false;
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uint16_t orig, new;
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pci_block_user_cfg_access(pdev);
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pci_read_config_word(pdev, PCI_COMMAND, &orig);
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pci_write_config_word(pdev, PCI_COMMAND,
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orig ^ PCI_COMMAND_INTX_DISABLE);
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pci_read_config_word(pdev, PCI_COMMAND, &new);
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if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
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dev_err(&pdev->dev, "Command register changed from "
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"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
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} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
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mask_supported = true;
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pci_write_config_word(pdev, PCI_COMMAND, orig);
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}
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pci_unblock_user_cfg_access(pdev);
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return mask_supported;
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}
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static bool pci_check_and_mask_intx(struct pci_dev *pdev)
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{
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bool pending;
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uint32_t status;
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pci_block_user_cfg_access(pdev);
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pci_read_config_dword(pdev, PCI_COMMAND, &status);
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/* interrupt is not ours, goes to out */
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pending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);
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if (pending) {
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uint16_t old, new;
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old = status;
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if (status != 0)
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new = old & (~PCI_COMMAND_INTX_DISABLE);
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else
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new = old | PCI_COMMAND_INTX_DISABLE;
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if (old != new)
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pci_write_config_word(pdev, PCI_COMMAND, new);
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}
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pci_unblock_user_cfg_access(pdev);
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return pending;
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}
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#endif /* < 3.3.0 */
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
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#define HAVE_PCI_IS_BRIDGE_API 1
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#endif
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
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#define HAVE_MSI_LIST_IN_GENERIC_DEVICE 1
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#endif
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)
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#define HAVE_PCI_MSI_MASK_IRQ 1
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#endif
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)
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#define HAVE_ALLOC_IRQ_VECTORS 1
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#endif
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static inline bool igbuio_kernel_is_locked_down(void)
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{
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#ifdef CONFIG_LOCK_DOWN_KERNEL
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#ifdef CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT
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return kernel_is_locked_down(NULL);
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#elif defined(CONFIG_EFI_SECURE_BOOT_LOCK_DOWN)
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return kernel_is_locked_down();
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#else
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return false;
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#endif
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#else
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return false;
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#endif
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}
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#ifndef fallthrough
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#ifndef __has_attribute
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#define __has_attribute(x) 0
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#endif
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#if __has_attribute(__fallthrough__)
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#define fallthrough __attribute__((__fallthrough__))
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#else
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#define fallthrough do {} while (0) /* fallthrough */
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#endif
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#endif
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@ -0,0 +1,668 @@
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// SPDX-License-Identifier: GPL-2.0
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/*-
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* Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/uio_driver.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/version.h>
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#include <linux/slab.h>
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/**
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* These enum and macro definitions are copied from the
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* file rte_pci_dev_features.h
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*/
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enum rte_intr_mode {
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RTE_INTR_MODE_NONE = 0,
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RTE_INTR_MODE_LEGACY,
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RTE_INTR_MODE_MSI,
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RTE_INTR_MODE_MSIX
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};
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#define RTE_INTR_MODE_NONE_NAME "none"
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#define RTE_INTR_MODE_LEGACY_NAME "legacy"
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#define RTE_INTR_MODE_MSI_NAME "msi"
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#define RTE_INTR_MODE_MSIX_NAME "msix"
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#include "compat.h"
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/**
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* A structure describing the private information for a uio device.
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*/
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struct rte_uio_pci_dev {
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struct uio_info info;
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struct pci_dev *pdev;
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enum rte_intr_mode mode;
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atomic_t refcnt;
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};
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static int wc_activate;
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static char *intr_mode;
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static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
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/* sriov sysfs */
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static ssize_t
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show_max_vfs(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
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}
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static ssize_t
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store_max_vfs(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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int err = 0;
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unsigned long max_vfs;
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struct pci_dev *pdev = to_pci_dev(dev);
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if (0 != kstrtoul(buf, 0, &max_vfs))
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return -EINVAL;
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if (0 == max_vfs)
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pci_disable_sriov(pdev);
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else if (0 == pci_num_vf(pdev))
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err = pci_enable_sriov(pdev, max_vfs);
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else /* do nothing if change max_vfs number */
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err = -EINVAL;
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return err ? err : count;
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}
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static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
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static struct attribute *dev_attrs[] = {
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&dev_attr_max_vfs.attr,
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NULL,
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};
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static const struct attribute_group dev_attr_grp = {
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.attrs = dev_attrs,
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};
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#ifndef HAVE_PCI_MSI_MASK_IRQ
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/*
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* It masks the msix on/off of generating MSI-X messages.
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*/
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static void
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igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
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{
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u32 mask_bits = desc->masked;
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unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL;
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if (state != 0)
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mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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else
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mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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if (mask_bits != desc->masked) {
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writel(mask_bits, desc->mask_base + offset);
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readl(desc->mask_base);
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desc->masked = mask_bits;
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}
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}
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/*
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* It masks the msi on/off of generating MSI messages.
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*/
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static void
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igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
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{
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u32 mask_bits = desc->masked;
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u32 offset = desc->irq - pdev->irq;
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u32 mask = 1 << offset;
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if (!desc->msi_attrib.maskbit)
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return;
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if (state != 0)
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mask_bits &= ~mask;
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else
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mask_bits |= mask;
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if (mask_bits != desc->masked) {
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pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
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desc->masked = mask_bits;
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}
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}
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static void
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igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
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{
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struct msi_desc *desc;
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struct list_head *msi_list;
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#ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
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msi_list = &pdev->dev.msi_list;
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#else
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msi_list = &pdev->msi_list;
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#endif
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if (mode == RTE_INTR_MODE_MSIX) {
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list_for_each_entry(desc, msi_list, list)
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igbuio_msix_mask_irq(desc, irq_state);
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} else if (mode == RTE_INTR_MODE_MSI) {
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list_for_each_entry(desc, msi_list, list)
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igbuio_msi_mask_irq(pdev, desc, irq_state);
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}
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}
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#endif
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/**
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* This is the irqcontrol callback to be registered to uio_info.
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* It can be used to disable/enable interrupt from user space processes.
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*
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* @param info
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* pointer to uio_info.
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* @param irq_state
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* state value. 1 to enable interrupt, 0 to disable interrupt.
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*
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* @return
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* - On success, 0.
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* - On failure, a negative value.
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*/
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static int
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igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
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{
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struct rte_uio_pci_dev *udev = info->priv;
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struct pci_dev *pdev = udev->pdev;
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#ifdef HAVE_PCI_MSI_MASK_IRQ
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struct irq_data *irq = irq_get_irq_data(udev->info.irq);
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#endif
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pci_cfg_access_lock(pdev);
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if (udev->mode == RTE_INTR_MODE_MSIX || udev->mode == RTE_INTR_MODE_MSI) {
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#ifdef HAVE_PCI_MSI_MASK_IRQ
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if (irq_state == 1)
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pci_msi_unmask_irq(irq);
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else
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pci_msi_mask_irq(irq);
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#else
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igbuio_mask_irq(pdev, udev->mode, irq_state);
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#endif
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}
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if (udev->mode == RTE_INTR_MODE_LEGACY)
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pci_intx(pdev, !!irq_state);
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pci_cfg_access_unlock(pdev);
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return 0;
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}
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/**
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* This is interrupt handler which will check if the interrupt is for the right device.
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* If yes, disable it here and will be enable later.
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*/
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static irqreturn_t
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igbuio_pci_irqhandler(int irq, void *dev_id)
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{
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struct rte_uio_pci_dev *udev = (struct rte_uio_pci_dev *)dev_id;
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struct uio_info *info = &udev->info;
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/* Legacy mode need to mask in hardware */
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if (udev->mode == RTE_INTR_MODE_LEGACY &&
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!pci_check_and_mask_intx(udev->pdev))
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return IRQ_NONE;
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uio_event_notify(info);
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/* Message signal mode, no share IRQ and automasked */
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return IRQ_HANDLED;
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}
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static int
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igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev)
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{
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int err = 0;
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#ifndef HAVE_ALLOC_IRQ_VECTORS
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struct msix_entry msix_entry;
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#endif
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switch (igbuio_intr_mode_preferred) {
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case RTE_INTR_MODE_MSIX:
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/* Only 1 msi-x vector needed */
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#ifndef HAVE_ALLOC_IRQ_VECTORS
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msix_entry.entry = 0;
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if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {
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dev_dbg(&udev->pdev->dev, "using MSI-X");
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udev->info.irq_flags = IRQF_NO_THREAD;
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udev->info.irq = msix_entry.vector;
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udev->mode = RTE_INTR_MODE_MSIX;
|
||||
break;
|
||||
}
|
||||
#else
|
||||
if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {
|
||||
dev_dbg(&udev->pdev->dev, "using MSI-X");
|
||||
udev->info.irq_flags = IRQF_NO_THREAD;
|
||||
udev->info.irq = pci_irq_vector(udev->pdev, 0);
|
||||
udev->mode = RTE_INTR_MODE_MSIX;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
fallthrough;
|
||||
case RTE_INTR_MODE_MSI:
|
||||
#ifndef HAVE_ALLOC_IRQ_VECTORS
|
||||
if (pci_enable_msi(udev->pdev) == 0) {
|
||||
dev_dbg(&udev->pdev->dev, "using MSI");
|
||||
udev->info.irq_flags = IRQF_NO_THREAD;
|
||||
udev->info.irq = udev->pdev->irq;
|
||||
udev->mode = RTE_INTR_MODE_MSI;
|
||||
break;
|
||||
}
|
||||
#else
|
||||
if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {
|
||||
dev_dbg(&udev->pdev->dev, "using MSI");
|
||||
udev->info.irq_flags = IRQF_NO_THREAD;
|
||||
udev->info.irq = pci_irq_vector(udev->pdev, 0);
|
||||
udev->mode = RTE_INTR_MODE_MSI;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
fallthrough;
|
||||
case RTE_INTR_MODE_LEGACY:
|
||||
if (pci_intx_mask_supported(udev->pdev)) {
|
||||
dev_dbg(&udev->pdev->dev, "using INTX");
|
||||
udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
|
||||
udev->info.irq = udev->pdev->irq;
|
||||
udev->mode = RTE_INTR_MODE_LEGACY;
|
||||
break;
|
||||
}
|
||||
dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");
|
||||
fallthrough;
|
||||
case RTE_INTR_MODE_NONE:
|
||||
udev->mode = RTE_INTR_MODE_NONE;
|
||||
udev->info.irq = UIO_IRQ_NONE;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(&udev->pdev->dev, "invalid IRQ mode %u",
|
||||
igbuio_intr_mode_preferred);
|
||||
udev->info.irq = UIO_IRQ_NONE;
|
||||
err = -EINVAL;
|
||||
}
|
||||
|
||||
if (udev->info.irq != UIO_IRQ_NONE)
|
||||
err = request_irq(udev->info.irq, igbuio_pci_irqhandler,
|
||||
udev->info.irq_flags, udev->info.name,
|
||||
udev);
|
||||
dev_info(&udev->pdev->dev, "uio device registered with irq %ld\n",
|
||||
udev->info.irq);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void
|
||||
igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev)
|
||||
{
|
||||
if (udev->info.irq) {
|
||||
free_irq(udev->info.irq, udev);
|
||||
udev->info.irq = 0;
|
||||
}
|
||||
|
||||
#ifndef HAVE_ALLOC_IRQ_VECTORS
|
||||
if (udev->mode == RTE_INTR_MODE_MSIX)
|
||||
pci_disable_msix(udev->pdev);
|
||||
if (udev->mode == RTE_INTR_MODE_MSI)
|
||||
pci_disable_msi(udev->pdev);
|
||||
#else
|
||||
if (udev->mode == RTE_INTR_MODE_MSIX ||
|
||||
udev->mode == RTE_INTR_MODE_MSI)
|
||||
pci_free_irq_vectors(udev->pdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* This gets called while opening uio device file.
|
||||
*/
|
||||
static int
|
||||
igbuio_pci_open(struct uio_info *info, struct inode *inode)
|
||||
{
|
||||
struct rte_uio_pci_dev *udev = info->priv;
|
||||
struct pci_dev *dev = udev->pdev;
|
||||
int err;
|
||||
|
||||
if (atomic_inc_return(&udev->refcnt) != 1)
|
||||
return 0;
|
||||
|
||||
/* set bus master, which was cleared by the reset function */
|
||||
pci_set_master(dev);
|
||||
|
||||
/* enable interrupts */
|
||||
err = igbuio_pci_enable_interrupts(udev);
|
||||
if (err) {
|
||||
atomic_dec(&udev->refcnt);
|
||||
dev_err(&dev->dev, "Enable interrupt fails\n");
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
igbuio_pci_release(struct uio_info *info, struct inode *inode)
|
||||
{
|
||||
struct rte_uio_pci_dev *udev = info->priv;
|
||||
struct pci_dev *dev = udev->pdev;
|
||||
|
||||
if (atomic_dec_and_test(&udev->refcnt)) {
|
||||
/* disable interrupts */
|
||||
igbuio_pci_disable_interrupts(udev);
|
||||
|
||||
/* stop the device from further DMA */
|
||||
pci_clear_master(dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Remap pci resources described by bar #pci_bar in uio resource n. */
|
||||
static int
|
||||
igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
|
||||
int n, int pci_bar, const char *name)
|
||||
{
|
||||
unsigned long addr, len;
|
||||
void *internal_addr;
|
||||
|
||||
if (n >= ARRAY_SIZE(info->mem))
|
||||
return -EINVAL;
|
||||
|
||||
addr = pci_resource_start(dev, pci_bar);
|
||||
len = pci_resource_len(dev, pci_bar);
|
||||
if (addr == 0 || len == 0)
|
||||
return -1;
|
||||
if (wc_activate == 0) {
|
||||
internal_addr = ioremap(addr, len);
|
||||
if (internal_addr == NULL)
|
||||
return -1;
|
||||
} else {
|
||||
internal_addr = NULL;
|
||||
}
|
||||
info->mem[n].name = name;
|
||||
info->mem[n].addr = addr;
|
||||
info->mem[n].internal_addr = internal_addr;
|
||||
info->mem[n].size = len;
|
||||
info->mem[n].memtype = UIO_MEM_PHYS;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get pci port io resources described by bar #pci_bar in uio resource n. */
|
||||
static int
|
||||
igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
|
||||
int n, int pci_bar, const char *name)
|
||||
{
|
||||
unsigned long addr, len;
|
||||
|
||||
if (n >= ARRAY_SIZE(info->port))
|
||||
return -EINVAL;
|
||||
|
||||
addr = pci_resource_start(dev, pci_bar);
|
||||
len = pci_resource_len(dev, pci_bar);
|
||||
if (addr == 0 || len == 0)
|
||||
return -EINVAL;
|
||||
|
||||
info->port[n].name = name;
|
||||
info->port[n].start = addr;
|
||||
info->port[n].size = len;
|
||||
info->port[n].porttype = UIO_PORT_X86;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Unmap previously ioremap'd resources */
|
||||
static void
|
||||
igbuio_pci_release_iomem(struct uio_info *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_UIO_MAPS; i++) {
|
||||
if (info->mem[i].internal_addr)
|
||||
iounmap(info->mem[i].internal_addr);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
|
||||
{
|
||||
int i, iom, iop, ret;
|
||||
unsigned long flags;
|
||||
static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
|
||||
"BAR0",
|
||||
"BAR1",
|
||||
"BAR2",
|
||||
"BAR3",
|
||||
"BAR4",
|
||||
"BAR5",
|
||||
};
|
||||
|
||||
iom = 0;
|
||||
iop = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
|
||||
if (pci_resource_len(dev, i) != 0 &&
|
||||
pci_resource_start(dev, i) != 0) {
|
||||
flags = pci_resource_flags(dev, i);
|
||||
if (flags & IORESOURCE_MEM) {
|
||||
ret = igbuio_pci_setup_iomem(dev, info, iom,
|
||||
i, bar_names[i]);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
iom++;
|
||||
} else if (flags & IORESOURCE_IO) {
|
||||
ret = igbuio_pci_setup_ioport(dev, info, iop,
|
||||
i, bar_names[i]);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
iop++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (iom != 0 || iop != 0) ? ret : -ENOENT;
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
|
||||
static int __devinit
|
||||
#else
|
||||
static int
|
||||
#endif
|
||||
igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
{
|
||||
struct rte_uio_pci_dev *udev;
|
||||
dma_addr_t map_dma_addr;
|
||||
void *map_addr;
|
||||
int err;
|
||||
|
||||
#ifdef HAVE_PCI_IS_BRIDGE_API
|
||||
if (pci_is_bridge(dev)) {
|
||||
dev_warn(&dev->dev, "Ignoring PCI bridge device\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
|
||||
if (!udev)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* enable device: ask low-level code to enable I/O and
|
||||
* memory
|
||||
*/
|
||||
err = pci_enable_device(dev);
|
||||
if (err != 0) {
|
||||
dev_err(&dev->dev, "Cannot enable PCI device\n");
|
||||
goto fail_free;
|
||||
}
|
||||
|
||||
/* enable bus mastering on the device */
|
||||
pci_set_master(dev);
|
||||
|
||||
/* remap IO memory */
|
||||
err = igbuio_setup_bars(dev, &udev->info);
|
||||
if (err != 0)
|
||||
goto fail_release_iomem;
|
||||
|
||||
/* set 64-bit DMA mask */
|
||||
err = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64));
|
||||
if (err != 0) {
|
||||
dev_err(&dev->dev, "Cannot set DMA mask\n");
|
||||
goto fail_release_iomem;
|
||||
}
|
||||
|
||||
/* fill uio infos */
|
||||
udev->info.name = "igb_uio";
|
||||
udev->info.version = "0.1";
|
||||
udev->info.irqcontrol = igbuio_pci_irqcontrol;
|
||||
udev->info.open = igbuio_pci_open;
|
||||
udev->info.release = igbuio_pci_release;
|
||||
udev->info.priv = udev;
|
||||
udev->pdev = dev;
|
||||
atomic_set(&udev->refcnt, 0);
|
||||
|
||||
err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
|
||||
if (err != 0)
|
||||
goto fail_release_iomem;
|
||||
|
||||
/* register uio driver */
|
||||
err = uio_register_device(&dev->dev, &udev->info);
|
||||
if (err != 0)
|
||||
goto fail_remove_group;
|
||||
|
||||
pci_set_drvdata(dev, udev);
|
||||
|
||||
/*
|
||||
* Doing a harmless dma mapping for attaching the device to
|
||||
* the iommu identity mapping if kernel boots with iommu=pt.
|
||||
* Note this is not a problem if no IOMMU at all.
|
||||
*/
|
||||
map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
|
||||
GFP_KERNEL);
|
||||
if (map_addr)
|
||||
memset(map_addr, 0, 1024);
|
||||
|
||||
if (!map_addr)
|
||||
dev_info(&dev->dev, "dma mapping failed\n");
|
||||
else {
|
||||
dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
|
||||
(unsigned long long)map_dma_addr, map_addr);
|
||||
|
||||
dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
|
||||
dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
|
||||
(unsigned long long)map_dma_addr, map_addr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail_remove_group:
|
||||
sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
|
||||
fail_release_iomem:
|
||||
igbuio_pci_release_iomem(&udev->info);
|
||||
pci_disable_device(dev);
|
||||
fail_free:
|
||||
kfree(udev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void
|
||||
igbuio_pci_remove(struct pci_dev *dev)
|
||||
{
|
||||
struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
|
||||
|
||||
igbuio_pci_release(&udev->info, NULL);
|
||||
|
||||
sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
|
||||
uio_unregister_device(&udev->info);
|
||||
igbuio_pci_release_iomem(&udev->info);
|
||||
pci_disable_device(dev);
|
||||
pci_set_drvdata(dev, NULL);
|
||||
kfree(udev);
|
||||
}
|
||||
|
||||
static int
|
||||
igbuio_config_intr_mode(char *intr_str)
|
||||
{
|
||||
if (!intr_str) {
|
||||
pr_info("Use MSIX interrupt by default\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
|
||||
igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
|
||||
pr_info("Use MSIX interrupt\n");
|
||||
} else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
|
||||
igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
|
||||
pr_info("Use MSI interrupt\n");
|
||||
} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
|
||||
igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
|
||||
pr_info("Use legacy interrupt\n");
|
||||
} else {
|
||||
pr_info("Error: bad parameter - %s\n", intr_str);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_driver igbuio_pci_driver = {
|
||||
.name = "igb_uio",
|
||||
.id_table = NULL,
|
||||
.probe = igbuio_pci_probe,
|
||||
.remove = igbuio_pci_remove,
|
||||
};
|
||||
|
||||
static int __init
|
||||
igbuio_pci_init_module(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (igbuio_kernel_is_locked_down()) {
|
||||
pr_err("Not able to use module, kernel lock down is enabled\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (wc_activate != 0)
|
||||
pr_info("wc_activate is set\n");
|
||||
|
||||
ret = igbuio_config_intr_mode(intr_mode);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return pci_register_driver(&igbuio_pci_driver);
|
||||
}
|
||||
|
||||
static void __exit
|
||||
igbuio_pci_exit_module(void)
|
||||
{
|
||||
pci_unregister_driver(&igbuio_pci_driver);
|
||||
}
|
||||
|
||||
module_init(igbuio_pci_init_module);
|
||||
module_exit(igbuio_pci_exit_module);
|
||||
|
||||
module_param(intr_mode, charp, S_IRUGO);
|
||||
MODULE_PARM_DESC(intr_mode,
|
||||
"igb_uio interrupt mode (default=msix):\n"
|
||||
" " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
|
||||
" " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
|
||||
" " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
|
||||
"\n");
|
||||
|
||||
module_param(wc_activate, int, 0);
|
||||
MODULE_PARM_DESC(wc_activate,
|
||||
"Activate support for write combining (WC) (default=0)\n"
|
||||
" 0 - disable\n"
|
||||
" other - enable\n");
|
||||
|
||||
MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright(c) 2017 Intel Corporation
|
||||
|
||||
mkfile = custom_target('igb_uio_makefile',
|
||||
output: 'Makefile',
|
||||
command: ['touch', '@OUTPUT@'])
|
||||
|
||||
custom_target('igb_uio',
|
||||
input: ['igb_uio.c', 'Kbuild'],
|
||||
output: 'igb_uio.ko',
|
||||
command: ['make', '-C', kernel_build_dir,
|
||||
'M=' + meson.current_build_dir(),
|
||||
'src=' + meson.current_source_dir(),
|
||||
'EXTRA_CFLAGS=-I' + meson.current_source_dir() +
|
||||
'/../../../lib/librte_eal/include',
|
||||
'modules'],
|
||||
depends: mkfile,
|
||||
install: true,
|
||||
install_dir: kernel_build_dir + '/extra/dpdk',
|
||||
build_by_default: get_option('enable_kmods'))
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright(c) 2018 Intel Corporation
|
||||
|
||||
subdirs = ['kni']
|
||||
subdirs = ['kni', 'igb_uio']
|
||||
|
||||
kernel_build_dir = get_option('kernel_dir')
|
||||
kernel_source_dir = get_option('kernel_dir')
|
||||
|
|
|
|||
|
|
@ -30,6 +30,22 @@ typedef cpuset_t rte_cpuset_t;
|
|||
#define RTE_HAS_CPUSET
|
||||
|
||||
#ifdef RTE_EAL_FREEBSD_CPUSET_LEGACY
|
||||
#if __FreeBSD_version >= 1301000
|
||||
#define RTE_CPU_AND(dst, src1, src2) do \
|
||||
{ \
|
||||
cpuset_t tmp; \
|
||||
CPU_COPY(src1, &tmp); \
|
||||
CPU_AND(&tmp, &tmp, src2); \
|
||||
CPU_COPY(&tmp, dst); \
|
||||
} while (0)
|
||||
#define RTE_CPU_OR(dst, src1, src2) do \
|
||||
{ \
|
||||
cpuset_t tmp; \
|
||||
CPU_COPY(src1, &tmp); \
|
||||
CPU_OR(&tmp, &tmp, src2); \
|
||||
CPU_COPY(&tmp, dst); \
|
||||
} while (0)
|
||||
#else
|
||||
#define RTE_CPU_AND(dst, src1, src2) do \
|
||||
{ \
|
||||
cpuset_t tmp; \
|
||||
|
|
@ -44,6 +60,7 @@ typedef cpuset_t rte_cpuset_t;
|
|||
CPU_OR(&tmp, src2); \
|
||||
CPU_COPY(&tmp, dst); \
|
||||
} while (0)
|
||||
#endif
|
||||
#define RTE_CPU_FILL(set) CPU_FILL(set)
|
||||
|
||||
/* In FreeBSD 13 CPU_NAND macro is CPU_ANDNOT */
|
||||
|
|
@ -56,6 +73,15 @@ typedef cpuset_t rte_cpuset_t;
|
|||
CPU_COPY(&tmp, dst); \
|
||||
} while (0)
|
||||
#else
|
||||
if __FreeBSD_version >= 1301000
|
||||
#define RTE_CPU_NOT(dst, src) do \
|
||||
{ \
|
||||
cpuset_t tmp; \
|
||||
CPU_FILL(&tmp); \
|
||||
CPU_ANDNOT(&tmp, &tmp, src); \
|
||||
CPU_COPY(&tmp, dst); \
|
||||
} while (0)
|
||||
#else
|
||||
#define RTE_CPU_NOT(dst, src) do \
|
||||
{ \
|
||||
cpuset_t tmp; \
|
||||
|
|
@ -63,6 +89,7 @@ typedef cpuset_t rte_cpuset_t;
|
|||
CPU_ANDNOT(&tmp, src); \
|
||||
CPU_COPY(&tmp, dst); \
|
||||
} while (0)
|
||||
#endif
|
||||
#endif /* CPU_NAND */
|
||||
|
||||
#else /* RTE_EAL_FREEBSD_CPUSET_LEGACY */
|
||||
|
|
|
|||
Loading…
Reference in New Issue