mirror of https://github.com/F-Stack/f-stack.git
80 lines
2.0 KiB
YAML
80 lines
2.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Reset Clock Controller Binding
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maintainers:
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- Gabriel Fernandez <gabriel.fernandez@st.com>
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description: |
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The RCC IP is both a reset and a clock controller.
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RCC makes also power management (resume/supend and wakeup interrupt).
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Please also refer to reset.txt for common reset controller binding usage.
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This binding uses common clock bindings
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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Specifying clocks
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=================
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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tree sources.
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Specifying softreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the reset device node and an index specifying
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which channel to use.
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The index is the bit number within the RCC registers bank, starting from RCC
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base address.
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
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Where bit_offset is the bit offset within the register.
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For example on STM32MP1, for LTDC reset:
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ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
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= 0x180 / 4 * 32 + 0 = 3072
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The list of valid indices for STM32MP1 is available in:
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include/dt-bindings/reset-controller/stm32mp1-resets.h
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This file implements defines like:
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#define LTDC_R 3072
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properties:
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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compatible:
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items:
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- const: st,stm32mp1-rcc
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- const: syscon
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reg:
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maxItems: 1
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required:
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- "#clock-cells"
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- "#reset-cells"
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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