2023-09-13 12:21:49 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 StarFive
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* Copyright(c) 2022 SiFive
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* Copyright(c) 2022 Semihalf
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*/
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#ifndef RTE_VECT_RISCV_H
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#define RTE_VECT_RISCV_H
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#include <stdint.h>
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#include "generic/rte_vect.h"
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#include "rte_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
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typedef int32_t xmm_t __attribute__((vector_size(16)));
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#define XMM_SIZE (sizeof(xmm_t))
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#define XMM_MASK (XMM_SIZE - 1)
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typedef union rte_xmm {
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xmm_t x;
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uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
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uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
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uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
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uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
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double pd[XMM_SIZE / sizeof(double)];
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2024-10-17 10:26:34 +00:00
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} __rte_aligned(16) rte_xmm_t;
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2023-09-13 12:21:49 +00:00
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static inline xmm_t
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vect_load_128(void *p)
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{
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xmm_t ret = *((xmm_t *)p);
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return ret;
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}
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static inline xmm_t
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vect_and(xmm_t data, xmm_t mask)
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{
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rte_xmm_t ret = {.x = data };
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rte_xmm_t m = {.x = mask };
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ret.u64[0] &= m.u64[0];
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ret.u64[1] &= m.u64[1];
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return ret.x;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* RTE_VECT_RISCV_H */
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