mirror of https://github.com/F-Stack/f-stack.git
56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014 IBM Corporation
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* Copyright(c) 2022 StarFive
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* Copyright(c) 2022 SiFive
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* Copyright(c) 2022 Semihalf
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*/
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#ifndef RTE_CPUFLAGS_RISCV_H
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#define RTE_CPUFLAGS_RISCV_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enumeration of all CPU features supported
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*/
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enum rte_cpu_flag_t {
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RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */
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RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */
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RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */
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RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point */
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RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */
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RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */
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RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */
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RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */
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RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */
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RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */
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RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */
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RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */
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RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */
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RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */
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RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */
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RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */
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RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */
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RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */
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RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */
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RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */
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RTE_CPUFLAG_RISCV_ISA_U, /* User mode */
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RTE_CPUFLAG_RISCV_ISA_V, /* Vector */
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RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */
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RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */
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RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */
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RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */
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/* The last item */
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RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
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};
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#include "generic/rte_cpuflags.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* RTE_CPUFLAGS_RISCV_H */
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