2021-02-05 08:48:47 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _IFCVF_OSDEP_H_
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#define _IFCVF_OSDEP_H_
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#include <stdint.h>
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#include <linux/pci_regs.h>
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#include <rte_cycles.h>
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#include <rte_pci.h>
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2023-09-13 12:21:49 +00:00
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#include <bus_pci_driver.h>
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2021-02-05 08:48:47 +00:00
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#include <rte_log.h>
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#include <rte_io.h>
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2022-09-06 04:00:10 +00:00
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#define WARNINGOUT(S, args...) RTE_LOG(WARNING, PMD, S, ##args)
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2021-02-05 08:48:47 +00:00
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#define DEBUGOUT(S, args...) RTE_LOG(DEBUG, PMD, S, ##args)
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#define STATIC static
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#define msec_delay(x) rte_delay_us_sleep(1000 * (x))
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#define IFCVF_READ_REG8(reg) rte_read8(reg)
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#define IFCVF_WRITE_REG8(val, reg) rte_write8((val), (reg))
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#define IFCVF_READ_REG16(reg) rte_read16(reg)
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#define IFCVF_WRITE_REG16(val, reg) rte_write16((val), (reg))
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#define IFCVF_READ_REG32(reg) rte_read32(reg)
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#define IFCVF_WRITE_REG32(val, reg) rte_write32((val), (reg))
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typedef struct rte_pci_device PCI_DEV;
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#define PCI_READ_CONFIG_BYTE(dev, val, where) \
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rte_pci_read_config(dev, val, 1, where)
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#define PCI_READ_CONFIG_DWORD(dev, val, where) \
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rte_pci_read_config(dev, val, 4, where)
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typedef uint8_t u8;
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typedef int8_t s8;
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typedef uint16_t u16;
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typedef int16_t s16;
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typedef uint32_t u32;
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typedef int32_t s32;
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typedef int64_t s64;
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typedef uint64_t u64;
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static inline int
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PCI_READ_CONFIG_RANGE(PCI_DEV *dev, uint32_t *val, int size, int where)
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{
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return rte_pci_read_config(dev, val, size, where);
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}
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#endif /* _IFCVF_OSDEP_H_ */
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