mirror of https://github.com/F-Stack/f-stack.git
286 lines
7.2 KiB
C
286 lines
7.2 KiB
C
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/******************************************************************************
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<EFBFBD> 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
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All rights reserved.
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This is proprietary source code of Freescale Semiconductor Inc.,
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and its use is subject to the NetComm Device Drivers EULA.
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The copyright notice above does not evidence any actual or intended
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publication of such source code.
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ALTERNATIVELY, redistribution and use in source and binary forms, with
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or without modification, are permitted provided that the following
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conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Freescale Semiconductor nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************/
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/******************************************************************************
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@File qman_private.h
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@Description QM private header
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*//***************************************************************************/
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#ifndef __QMAN_PRIVATE_H
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#define __QMAN_PRIVATE_H
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#include "fsl_qman.h"
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#define __ERR_MODULE__ MODULE_QM
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#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS)
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/* Optionally compile-in assertion-checking */
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#define QM_CHECKING
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#endif /* defined(DEBUG) || ... */
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/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers
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* and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
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* execution reordering with respect to other code/instructions that manipulate
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* the same cacheline. */
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#ifdef CORE_E500MC
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#if defined(_DIAB_TOOL)
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#define hwsync() \
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do { \
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__asm__ __volatile__ ("sync"); \
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} while(0)
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#define lwsync() \
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do { \
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__asm__ __volatile__ ("lwsync"); \
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} while(0)
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__asm__ __volatile__ void dcbf (volatile void * addr)
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{
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%reg addr
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dcbf r0, addr
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}
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__asm__ __volatile__ void dcbt_ro (volatile void * addr)
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{
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%reg addr
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dcbt r0, addr
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}
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__asm__ __volatile__ void dcbt_rw (volatile void * addr)
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{
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%reg addr
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dcbtst r0, addr
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}
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__asm__ __volatile__ void dcbzl (volatile void * addr)
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{
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%reg addr
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dcbzl r0, addr
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}
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#define dcbz_64(p) \
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do { \
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dcbzl(p); \
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} while (0)
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#define dcbf_64(p) \
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do { \
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dcbf(p); \
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} while (0)
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/* Commonly used combo */
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#define dcbit_ro(p) \
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do { \
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dcbi(p); \
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dcbt_ro(p); \
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} while (0)
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#else /* GNU C */
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#define hwsync() \
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do { \
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__asm__ __volatile__ ("sync" : : : "memory"); \
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} while(0)
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#define lwsync() \
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do { \
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__asm__ __volatile__ ("lwsync" : : : "memory"); \
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} while(0)
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#define dcbf(addr) \
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do { \
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__asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
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} while(0)
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#define dcbt_ro(addr) \
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do { \
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__asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
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} while(0)
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#define dcbt_rw(addr) \
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do { \
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__asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \
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} while(0)
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#define dcbzl(p) \
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do { \
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__asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \
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} while(0)
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#define dcbz_64(p) \
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do { \
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dcbzl(p); \
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} while (0)
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#define dcbf_64(p) \
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do { \
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dcbf(p); \
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} while (0)
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/* Commonly used combo */
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#define dcbit_ro(p) \
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do { \
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dcbi(p); \
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dcbt_ro(p); \
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} while (0)
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#endif /* _DIAB_TOOL */
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#else
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#define hwsync CORE_MemoryBarrier
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#define lwsync hwsync
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#define dcbf(p) \
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do { \
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__asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \
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} while(0)
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#define dcbt_ro(p) \
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do { \
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__asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
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lwsync(); \
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} while(0)
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#define dcbt_rw(p) \
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do { \
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__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \
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} while(0)
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#define dcbz(p) \
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do { \
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__asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \
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} while (0)
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#define dcbz_64(p) \
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do { \
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dcbz((uint32_t)p + 32); \
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dcbz(p); \
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} while (0)
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#define dcbf_64(p) \
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do { \
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dcbf((uint32_t)p + 32); \
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dcbf(p); \
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} while (0)
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/* Commonly used combo */
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#define dcbit_ro(p) \
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do { \
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dcbi(p); \
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dcbi((uint32_t)p + 32); \
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dcbt_ro(p); \
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dcbt_ro((uint32_t)p + 32); \
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} while (0)
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#endif /* CORE_E500MC */
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#define dcbi(p) dcbf(p)
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struct qm_addr {
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void *addr_ce; /* cache-enabled */
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void *addr_ci; /* cache-inhibited */
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};
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/* EQCR state */
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struct qm_eqcr {
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struct qm_eqcr_entry *ring, *cursor;
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uint8_t ci, available, ithresh, vbit;
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#ifdef QM_CHECKING
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uint32_t busy;
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e_QmPortalProduceMode pmode;
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e_QmPortalEqcrConsumeMode cmode;
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#endif /* QM_CHECKING */
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};
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/* DQRR state */
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struct qm_dqrr {
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struct qm_dqrr_entry *ring, *cursor;
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uint8_t pi, ci, fill, ithresh, vbit, flags;
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#ifdef QM_CHECKING
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e_QmPortalDequeueMode dmode;
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e_QmPortalProduceMode pmode;
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e_QmPortalDqrrConsumeMode cmode;
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#endif /* QM_CHECKING */
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};
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#define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */
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#define QM_DQRR_FLAG_SE 0x02 /* Stash data */
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/* MR state */
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struct qm_mr {
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struct qm_mr_entry *ring, *cursor;
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uint8_t pi, ci, fill, ithresh, vbit;
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#ifdef QM_CHECKING
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e_QmPortalProduceMode pmode;
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e_QmPortalMrConsumeMode cmode;
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#endif /* QM_CHECKING */
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};
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/* MC state */
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struct qm_mc {
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struct qm_mc_command *cr;
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struct qm_mc_result *rr;
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uint8_t rridx, vbit;
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#ifdef QM_CHECKING
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enum {
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/* Can be _mc_start()ed */
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mc_idle,
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/* Can be _mc_commit()ed or _mc_abort()ed */
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mc_user,
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/* Can only be _mc_retry()ed */
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mc_hw
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} state;
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#endif /* QM_CHECKING */
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};
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/********************/
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/* Portal structure */
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/********************/
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struct qm_portal {
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/* In the non-QM_CHECKING case, everything up to and
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* including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a
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* cause for a concern. In other words, don't rearrange this structure
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* on a whim, there be dragons ... */
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struct qm_addr addr;
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struct qm_eqcr eqcr;
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struct qm_dqrr dqrr;
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struct qm_mr mr;
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struct qm_mc mc;
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struct qm_portal_config config;
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t_Handle bind_lock;
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/* Logical index (not cell-index) */
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int index;
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};
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#endif /* __QMAN_PRIVATE_H */
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