f-stack/dpdk/drivers/event/cnxk/cnxk_worker.h

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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(C) 2021 Marvell.
*/
#ifndef __CNXK_WORKER_H__
#define __CNXK_WORKER_H__
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#if defined(__aarch64__)
#include "roc_io.h"
#else
#include "roc_io_generic.h"
#endif
#include "cnxk_eventdev_dp.h"
#include "hw/ssow.h"
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/* SSO Operations */
static __rte_always_inline void
cnxk_sso_hws_add_work(const uint64_t event_ptr, const uint32_t tag,
const uint8_t new_tt, const uintptr_t grp_base)
{
uint64_t add_work0;
add_work0 = tag | ((uint64_t)(new_tt) << 32);
roc_store_pair(add_work0, event_ptr, grp_base);
}
static __rte_always_inline void
cnxk_sso_hws_swtag_desched(uint32_t tag, uint8_t new_tt, uint16_t grp,
uintptr_t swtag_desched_op)
{
uint64_t val;
val = tag | ((uint64_t)(new_tt & 0x3) << 32) | ((uint64_t)grp << 34);
__atomic_store_n((uint64_t *)swtag_desched_op, val, __ATOMIC_RELEASE);
}
static __rte_always_inline void
cnxk_sso_hws_swtag_norm(uint32_t tag, uint8_t new_tt, uintptr_t swtag_norm_op)
{
uint64_t val;
val = tag | ((uint64_t)(new_tt & 0x3) << 32);
plt_write64(val, swtag_norm_op);
}
static __rte_always_inline void
cnxk_sso_hws_swtag_untag(uintptr_t swtag_untag_op)
{
plt_write64(0, swtag_untag_op);
}
static __rte_always_inline void
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cnxk_sso_hws_swtag_flush(uint64_t base)
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{
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plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
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}
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static __rte_always_inline uint64_t
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cnxk_sso_hws_swtag_wait(uintptr_t tag_op)
{
uint64_t swtp;
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#ifdef RTE_ARCH_ARM64
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asm volatile(PLT_CPU_FEATURE_PREAMBLE
" ldr %[swtb], [%[swtp_loc]] \n"
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" tbz %[swtb], 62, .Ldone%= \n"
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" sevl \n"
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".Lrty%=: wfe \n"
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" ldr %[swtb], [%[swtp_loc]] \n"
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" tbnz %[swtb], 62, .Lrty%= \n"
".Ldone%=: \n"
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: [swtb] "=&r"(swtp)
: [swtp_loc] "r"(tag_op));
#else
/* Wait for the SWTAG/SWTAG_FULL operation */
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do {
swtp = plt_read64(tag_op);
} while (swtp & BIT_ULL(62));
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#endif
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return swtp;
}
static __rte_always_inline void
cnxk_sso_hws_desched(uint64_t u64, uint64_t base)
{
plt_write64(u64, base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
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}
#endif