mirror of https://github.com/F-Stack/f-stack.git
122 lines
5.0 KiB
C
122 lines
5.0 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2023 Intel Corporation
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*/
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#ifndef VRB2_VF_ENUM_H
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#define VRB2_VF_ENUM_H
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/*
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* VRB2 Register mapping on VF BAR0
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* This is automatically generated from RDL, format may change with new RDL
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*/
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enum {
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VRB2_VfHiVfToPfDbellVf = 0x00000000,
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VRB2_VfHiPfToVfDbellVf = 0x00000008,
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VRB2_VfHiInfoRingBaseLoVf = 0x00000010,
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VRB2_VfHiInfoRingBaseHiVf = 0x00000014,
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VRB2_VfHiInfoRingPointerVf = 0x00000018,
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VRB2_VfHiInfoRingIntWrEnVf = 0x00000020,
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VRB2_VfHiInfoRingPf2VfWrEnVf = 0x00000024,
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VRB2_VfHiMsixVectorMapperVf = 0x00000060,
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VRB2_VfHiDeviceStatus = 0x00000068,
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VRB2_VfHiInterruptSrc = 0x00000070,
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VRB2_VfDmaFec5GulDescBaseLoRegVf = 0x00000120,
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VRB2_VfDmaFec5GulDescBaseHiRegVf = 0x00000124,
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VRB2_VfDmaFec5GulRespPtrLoRegVf = 0x00000128,
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VRB2_VfDmaFec5GulRespPtrHiRegVf = 0x0000012C,
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VRB2_VfDmaFec5GdlDescBaseLoRegVf = 0x00000140,
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VRB2_VfDmaFec5GdlDescBaseHiRegVf = 0x00000144,
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VRB2_VfDmaFec5GdlRespPtrLoRegVf = 0x00000148,
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VRB2_VfDmaFec5GdlRespPtrHiRegVf = 0x0000014C,
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VRB2_VfDmaFec4GulDescBaseLoRegVf = 0x00000160,
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VRB2_VfDmaFec4GulDescBaseHiRegVf = 0x00000164,
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VRB2_VfDmaFec4GulRespPtrLoRegVf = 0x00000168,
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VRB2_VfDmaFec4GulRespPtrHiRegVf = 0x0000016C,
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VRB2_VfDmaFec4GdlDescBaseLoRegVf = 0x00000180,
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VRB2_VfDmaFec4GdlDescBaseHiRegVf = 0x00000184,
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VRB2_VfDmaFec4GdlRespPtrLoRegVf = 0x00000188,
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VRB2_VfDmaFec4GdlRespPtrHiRegVf = 0x0000018C,
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VRB2_VfDmaFftDescBaseLoRegVf = 0x000001A0,
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VRB2_VfDmaFftDescBaseHiRegVf = 0x000001A4,
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VRB2_VfDmaFftRespPtrLoRegVf = 0x000001A8,
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VRB2_VfDmaFftRespPtrHiRegVf = 0x000001AC,
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VRB2_VfDmaMldDescBaseLoRegVf = 0x000001C0,
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VRB2_VfDmaMldDescBaseHiRegVf = 0x000001C4,
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VRB2_VfDmaMldRespPtrLoRegVf = 0x000001C8,
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VRB2_VfDmaMldRespPtrHiRegVf = 0x000001CC,
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VRB2_VfPmACntrlRegVf = 0x00000200,
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VRB2_VfPmACountVf = 0x00000208,
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VRB2_VfPmAKCntLoVf = 0x00000210,
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VRB2_VfPmAKCntHiVf = 0x00000214,
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VRB2_VfPmADeltaCntLoVf = 0x00000220,
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VRB2_VfPmADeltaCntHiVf = 0x00000224,
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VRB2_VfPmBCntrlRegVf = 0x00000240,
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VRB2_VfPmBCountVf = 0x00000248,
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VRB2_VfPmBKCntLoVf = 0x00000250,
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VRB2_VfPmBKCntHiVf = 0x00000254,
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VRB2_VfPmBDeltaCntLoVf = 0x00000260,
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VRB2_VfPmBDeltaCntHiVf = 0x00000264,
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VRB2_VfPmCCntrlRegVf = 0x00000280,
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VRB2_VfPmCCountVf = 0x00000288,
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VRB2_VfPmCKCntLoVf = 0x00000290,
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VRB2_VfPmCKCntHiVf = 0x00000294,
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VRB2_VfPmCDeltaCntLoVf = 0x000002A0,
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VRB2_VfPmCDeltaCntHiVf = 0x000002A4,
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VRB2_VfPmDCntrlRegVf = 0x000002C0,
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VRB2_VfPmDCountVf = 0x000002C8,
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VRB2_VfPmDKCntLoVf = 0x000002D0,
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VRB2_VfPmDKCntHiVf = 0x000002D4,
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VRB2_VfPmDDeltaCntLoVf = 0x000002E0,
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VRB2_VfPmDDeltaCntHiVf = 0x000002E4,
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VRB2_VfPmECntrlRegVf = 0x00000300,
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VRB2_VfPmECountVf = 0x00000308,
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VRB2_VfPmEKCntLoVf = 0x00000310,
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VRB2_VfPmEKCntHiVf = 0x00000314,
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VRB2_VfPmEDeltaCntLoVf = 0x00000320,
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VRB2_VfPmEDeltaCntHiVf = 0x00000324,
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VRB2_VfPmFCntrlRegVf = 0x00000340,
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VRB2_VfPmFCountVf = 0x00000348,
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VRB2_VfPmFKCntLoVf = 0x00000350,
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VRB2_VfPmFKCntHiVf = 0x00000354,
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VRB2_VfPmFDeltaCntLoVf = 0x00000360,
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VRB2_VfPmFDeltaCntHiVf = 0x00000364,
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VRB2_VfQmgrAqReset0 = 0x00000600,
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VRB2_VfQmgrAqReset1 = 0x00000604,
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VRB2_VfQmgrAqReset2 = 0x00000608,
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VRB2_VfQmgrAqReset3 = 0x0000060C,
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VRB2_VfQmgrRingSizeVf = 0x00000610,
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VRB2_VfQmgrGrpDepthLog20Vf = 0x00000620,
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VRB2_VfQmgrGrpDepthLog21Vf = 0x00000624,
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VRB2_VfQmgrGrpDepthLog22Vf = 0x00000628,
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VRB2_VfQmgrGrpDepthLog23Vf = 0x0000062C,
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VRB2_VfQmgrGrpFunction0Vf = 0x00000630,
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VRB2_VfQmgrGrpFunction1Vf = 0x00000634,
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VRB2_VfQmgrAramUsageN0 = 0x00000640,
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VRB2_VfQmgrAramUsageN1 = 0x00000644,
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VRB2_VfQmgrAramUsageN2 = 0x00000648,
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VRB2_VfQmgrAramUsageN3 = 0x0000064C,
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VRB2_VfHiMSIXBaseLoRegVf = 0x00001000,
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VRB2_VfHiMSIXBaseHiRegVf = 0x00001004,
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VRB2_VfHiMSIXBaseDataRegVf = 0x00001008,
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VRB2_VfHiMSIXBaseMaskRegVf = 0x0000100C,
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VRB2_VfHiMSIXPBABaseLoRegVf = 0x00003000,
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VRB2_VfQmgrIngressAq = 0x00004000,
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};
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/* TIP VF Interrupt numbers */
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enum {
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VRB2_VF_INT_QMGR_AQ_OVERFLOW = 0,
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VRB2_VF_INT_DOORBELL_PF_2_VF = 1,
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VRB2_VF_INT_ILLEGAL_FORMAT = 2,
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VRB2_VF_INT_QMGR_DISABLED_ACCESS = 3,
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VRB2_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
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VRB2_VF_INT_DMA_DL_DESC_IRQ = 5,
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VRB2_VF_INT_DMA_UL_DESC_IRQ = 6,
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VRB2_VF_INT_DMA_FFT_DESC_IRQ = 7,
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VRB2_VF_INT_DMA_UL5G_DESC_IRQ = 8,
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VRB2_VF_INT_DMA_DL5G_DESC_IRQ = 9,
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VRB2_VF_INT_DMA_MLD_DESC_IRQ = 10,
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};
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#endif /* VRB2_VF_ENUM_H */
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