2019-01-18 09:27:45 +00:00
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/*-
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* BSD LICENSE
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2018-05-15 09:49:22 +00:00
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*
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* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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2019-01-18 09:27:45 +00:00
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* Copyright 2016 NXP.
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2018-05-15 09:49:22 +00:00
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*
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2019-01-18 09:27:45 +00:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Freescale Semiconductor, Inc nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2018-05-15 09:49:22 +00:00
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*/
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#ifndef _DPAA2_HW_DPBP_H_
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#define _DPAA2_HW_DPBP_H_
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#define DPAA2_MAX_BUF_POOLS 8
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struct buf_pool_cfg {
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void *addr;
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/**< The address from where DPAA2 will carve out the buffers */
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rte_iova_t phys_addr;
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/**< Physical address of the memory provided in addr */
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uint32_t num;
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/**< Number of buffers */
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uint32_t size;
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/**< Size including headroom for each buffer */
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uint16_t align;
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/**< Buffer alignment (in bytes) */
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uint16_t bpid;
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/**< Autogenerated buffer pool ID for internal use */
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};
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struct buf_pool {
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uint32_t size; /**< Size of the Pool */
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uint32_t num_bufs; /**< Number of buffers in Pool */
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uint16_t bpid; /**< Pool ID, from pool configuration */
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uint8_t *h_bpool_mem; /**< Internal context data */
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struct dpaa2_dpbp_dev *dpbp_node; /**< Hardware context */
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};
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/*!
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* Buffer pool list configuration structure. User need to give DPAA2 the
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* valid number of 'num_buf_pools'.
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*/
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struct dpaa2_bp_list_cfg {
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struct buf_pool_cfg buf_pool; /* Configuration of each buffer pool*/
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};
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struct dpaa2_bp_list {
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struct dpaa2_bp_list *next;
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struct rte_mempool *mp; /**< DPDK RTE EAL pool reference */
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int32_t dpaa2_ops_index; /**< Index into DPDK Mempool ops table */
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struct buf_pool buf_pool;
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};
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struct dpaa2_bp_info {
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uint32_t meta_data_size;
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uint32_t bpid;
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struct dpaa2_bp_list *bp_list;
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};
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#define mempool_to_bpinfo(mp) ((struct dpaa2_bp_info *)(mp)->pool_data)
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#define mempool_to_bpid(mp) ((mempool_to_bpinfo(mp))->bpid)
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extern struct dpaa2_bp_info rte_dpaa2_bpid_info[MAX_BPID];
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int rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
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void **obj_table, unsigned int count);
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#endif /* _DPAA2_HW_DPBP_H_ */
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