mirror of https://github.com/F-Stack/f-stack.git
94 lines
2.0 KiB
C
94 lines
2.0 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015 RehiveTech. All rights reserved.
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*/
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#ifndef _RTE_CYCLES_ARM32_H_
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#define _RTE_CYCLES_ARM32_H_
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/* ARM v7 does not have suitable source of clock signals. The only clock counter
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available in the core is 32 bit wide. Therefore it is unsuitable as the
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counter overlaps every few seconds and probably is not accessible by
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userspace programs. Therefore we use clock_gettime(CLOCK_MONOTONIC_RAW) to
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simulate counter running at 1GHz.
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*/
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#include <time.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "generic/rte_cycles.h"
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/**
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* Read the time base register.
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*
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* @return
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* The time base for this lcore.
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*/
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#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
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/**
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* This call is easily portable to any architecture, however,
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* it may require a system call and imprecise for some tasks.
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*/
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static inline uint64_t
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__rte_rdtsc_syscall(void)
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{
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struct timespec val;
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uint64_t v;
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while (clock_gettime(CLOCK_MONOTONIC_RAW, &val) != 0)
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/* no body */;
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v = (uint64_t) val.tv_sec * 1000000000LL;
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v += (uint64_t) val.tv_nsec;
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return v;
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}
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#define rte_rdtsc __rte_rdtsc_syscall
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#else
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/**
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* This function requires to configure the PMCCNTR and enable
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* userspace access to it:
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*
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* asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(1));
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* asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(29));
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* asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(0x8000000f));
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*
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* which is possible only from the privileged mode (kernel space).
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*/
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static inline uint64_t
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__rte_rdtsc_pmccntr(void)
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{
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unsigned tsc;
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uint64_t final_tsc;
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/* Read PMCCNTR */
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asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(tsc));
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/* 1 tick = 64 clocks */
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final_tsc = ((uint64_t)tsc) << 6;
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return (uint64_t)final_tsc;
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}
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#define rte_rdtsc __rte_rdtsc_pmccntr
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#endif /* RTE_ARM_EAL_RDTSC_USE_PMU */
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static inline uint64_t
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rte_rdtsc_precise(void)
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{
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rte_mb();
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return rte_rdtsc();
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}
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static inline uint64_t
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rte_get_tsc_cycles(void) { return rte_rdtsc(); }
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_CYCLES_ARM32_H_ */
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