2021-08-31 11:00:09 +00:00
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/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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2017-04-21 10:43:26 +00:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2021-08-31 11:00:09 +00:00
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2017-04-21 10:43:26 +00:00
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/******************************************************************************
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@File fm.h
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@Description FM internal structures and definitions.
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*//***************************************************************************/
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#ifndef __FM_H
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#define __FM_H
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#include "error_ext.h"
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#include "std_ext.h"
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#include "fm_ext.h"
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#include "fm_ipc.h"
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2021-08-31 11:00:09 +00:00
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#include "fsl_fman.h"
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2017-04-21 10:43:26 +00:00
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#define __ERR_MODULE__ MODULE_FM
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#define FM_MAX_NUM_OF_HW_PORT_IDS 64
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#define FM_MAX_NUM_OF_GUESTS 100
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/**************************************************************************//**
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@Description Exceptions
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*//***************************************************************************/
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#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */
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#define FM_EX_DMA_READ_ECC 0x40000000
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#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000
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#define FM_EX_DMA_FM_WRITE_ECC 0x10000000
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#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */
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#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */
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#define FM_EX_FPM_DOUBLE_ECC 0x02000000
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#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */
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#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */
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#define FM_EX_QMI_DOUBLE_ECC 0x00400000
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#define FM_EX_BMI_LIST_RAM_ECC 0x00200000
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2021-08-31 11:00:09 +00:00
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#define FM_EX_BMI_STORAGE_PROFILE_ECC 0x00100000
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2017-04-21 10:43:26 +00:00
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#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000
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#define FM_EX_IRAM_ECC 0x00040000
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2021-08-31 11:00:09 +00:00
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#define FM_EX_MURAM_ECC 0x00020000
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2017-04-21 10:43:26 +00:00
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#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000
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2021-08-31 11:00:09 +00:00
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#define FM_EX_DMA_SINGLE_PORT_ECC 0x00008000
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#define DMA_EMSR_EMSTR_MASK 0x0000FFFF
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#define DMA_THRESH_COMMQ_MASK 0xFF000000
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#define DMA_THRESH_READ_INT_BUF_MASK 0x007F0000
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#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000007F
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#define GET_EXCEPTION_FLAG(bitMask, exception) \
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switch (exception){ \
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case e_FM_EX_DMA_BUS_ERROR: \
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bitMask = FM_EX_DMA_BUS_ERROR; break; \
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case e_FM_EX_DMA_SINGLE_PORT_ECC: \
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bitMask = FM_EX_DMA_SINGLE_PORT_ECC; break; \
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case e_FM_EX_DMA_READ_ECC: \
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bitMask = FM_EX_DMA_READ_ECC; break; \
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case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \
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bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \
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case e_FM_EX_DMA_FM_WRITE_ECC: \
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bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \
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case e_FM_EX_FPM_STALL_ON_TASKS: \
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bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \
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case e_FM_EX_FPM_SINGLE_ECC: \
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bitMask = FM_EX_FPM_SINGLE_ECC; break; \
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case e_FM_EX_FPM_DOUBLE_ECC: \
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bitMask = FM_EX_FPM_DOUBLE_ECC; break; \
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case e_FM_EX_QMI_SINGLE_ECC: \
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bitMask = FM_EX_QMI_SINGLE_ECC; break; \
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case e_FM_EX_QMI_DOUBLE_ECC: \
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bitMask = FM_EX_QMI_DOUBLE_ECC; break; \
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case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \
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bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \
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case e_FM_EX_BMI_LIST_RAM_ECC: \
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bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \
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case e_FM_EX_BMI_STORAGE_PROFILE_ECC: \
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bitMask = FM_EX_BMI_STORAGE_PROFILE_ECC; break; \
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case e_FM_EX_BMI_STATISTICS_RAM_ECC: \
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bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \
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case e_FM_EX_BMI_DISPATCH_RAM_ECC: \
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bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \
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case e_FM_EX_IRAM_ECC: \
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bitMask = FM_EX_IRAM_ECC; break; \
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case e_FM_EX_MURAM_ECC: \
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bitMask = FM_EX_MURAM_ECC; break; \
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default: bitMask = 0;break; \
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}
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#define GET_FM_MODULE_EVENT(_mod, _id, _intrType, _event) \
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switch (_mod) { \
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case e_FM_MOD_PRS: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
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break; \
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case e_FM_MOD_KG: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
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break; \
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case e_FM_MOD_PLCR: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
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break; \
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case e_FM_MOD_TMR: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
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break; \
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case e_FM_MOD_10G_MAC: \
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if (_id >= FM_MAX_NUM_OF_10G_MACS) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_10G_MAC0 + _id) : (e_FM_EV_10G_MAC0 + _id); \
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break; \
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case e_FM_MOD_1G_MAC: \
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if (_id >= FM_MAX_NUM_OF_1G_MACS) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_1G_MAC0 + _id) : (e_FM_EV_1G_MAC0 + _id); \
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break; \
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case e_FM_MOD_MACSEC: \
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switch (_id){ \
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case (0): _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_MACSEC_MAC0:e_FM_EV_MACSEC_MAC0; \
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break; \
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} \
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break; \
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case e_FM_MOD_FMAN_CTRL: \
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if (_intrType == e_FM_INTR_TYPE_ERR) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (e_FM_EV_FMAN_CTRL_0 + _id); \
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break; \
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default: _event = e_FM_EV_DUMMY_LAST; \
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break; \
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}
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#define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \
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switch (_cache_override){ \
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case e_FM_DMA_NO_CACHE_OR: \
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fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
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case e_FM_DMA_NO_STASH_DATA: \
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fsl_cache_override = E_FMAN_DMA_NO_STASH_DATA; break; \
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case e_FM_DMA_MAY_STASH_DATA: \
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fsl_cache_override = E_FMAN_DMA_MAY_STASH_DATA; break; \
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case e_FM_DMA_STASH_DATA: \
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fsl_cache_override = E_FMAN_DMA_STASH_DATA; break; \
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default: \
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fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
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}
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#define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \
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switch (_aid_mode){ \
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case e_FM_DMA_AID_OUT_PORT_ID: \
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fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
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case e_FM_DMA_AID_OUT_TNUM: \
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fsl_aid_mode = E_FMAN_DMA_AID_OUT_TNUM; break; \
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default: \
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fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
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}
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#define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \
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switch (_dma_dbg_cnt){ \
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case e_FM_DMA_DBG_NO_CNT: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
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case e_FM_DMA_DBG_CNT_DONE: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_DONE; break; \
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case e_FM_DMA_DBG_CNT_COMM_Q_EM: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break; \
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case e_FM_DMA_DBG_CNT_INT_READ_EM: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_READ_EM; break; \
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case e_FM_DMA_DBG_CNT_INT_WRITE_EM: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break; \
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case e_FM_DMA_DBG_CNT_FPM_WAIT: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break; \
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case e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break; \
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case e_FM_DMA_DBG_CNT_RAW_WAR_PROT: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break; \
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default: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
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}
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#define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \
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switch (_dma_emer){ \
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case e_FM_DMA_EM_EBS: \
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fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
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case e_FM_DMA_EM_SOS: \
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fsl_dma_emer = E_FMAN_DMA_EM_SOS; break; \
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default: \
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fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
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}
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#define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \
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switch (_dma_err){ \
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case e_FM_DMA_ERR_CATASTROPHIC: \
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fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
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case e_FM_DMA_ERR_REPORT: \
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fsl_dma_err = E_FMAN_DMA_ERR_REPORT; break; \
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default: \
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fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
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}
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#define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \
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switch (_catastrophic_err){ \
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case e_FM_CATASTROPHIC_ERR_STALL_PORT: \
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fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
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case e_FM_CATASTROPHIC_ERR_STALL_TASK: \
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fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_TASK; break; \
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default: \
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fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
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}
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#define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \
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switch (_counters){ \
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case e_FM_COUNTERS_ENQ_TOTAL_FRAME: \
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fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
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case e_FM_COUNTERS_DEQ_TOTAL_FRAME: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break; \
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case e_FM_COUNTERS_DEQ_0: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_0; break; \
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case e_FM_COUNTERS_DEQ_1: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_1; break; \
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case e_FM_COUNTERS_DEQ_2: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_2; break; \
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case e_FM_COUNTERS_DEQ_3: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_3; break; \
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case e_FM_COUNTERS_DEQ_FROM_DEFAULT: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break; \
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case e_FM_COUNTERS_DEQ_FROM_CONTEXT: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break; \
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case e_FM_COUNTERS_DEQ_FROM_FD: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_FD; break; \
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case e_FM_COUNTERS_DEQ_CONFIRM: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_CONFIRM; break; \
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default: \
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fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
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}
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2017-04-21 10:43:26 +00:00
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/**************************************************************************//**
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@Description defaults
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*//***************************************************************************/
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2021-08-31 11:00:09 +00:00
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#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\
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2017-04-21 10:43:26 +00:00
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FM_EX_DMA_READ_ECC |\
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FM_EX_DMA_SYSTEM_WRITE_ECC |\
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FM_EX_DMA_FM_WRITE_ECC |\
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FM_EX_FPM_STALL_ON_TASKS |\
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FM_EX_FPM_SINGLE_ECC |\
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FM_EX_FPM_DOUBLE_ECC |\
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FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\
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FM_EX_BMI_LIST_RAM_ECC |\
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2021-08-31 11:00:09 +00:00
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FM_EX_BMI_STORAGE_PROFILE_ECC |\
|
2017-04-21 10:43:26 +00:00
|
|
|
FM_EX_BMI_STATISTICS_RAM_ECC |\
|
|
|
|
FM_EX_IRAM_ECC |\
|
2021-08-31 11:00:09 +00:00
|
|
|
FM_EX_MURAM_ECC |\
|
|
|
|
FM_EX_BMI_DISPATCH_RAM_ECC |\
|
|
|
|
FM_EX_QMI_DOUBLE_ECC |\
|
|
|
|
FM_EX_QMI_SINGLE_ECC)
|
|
|
|
|
2017-04-21 10:43:26 +00:00
|
|
|
#define DEFAULT_eccEnable FALSE
|
|
|
|
#ifdef FM_PEDANTIC_DMA
|
|
|
|
#define DEFAULT_aidOverride TRUE
|
|
|
|
#else
|
|
|
|
#define DEFAULT_aidOverride FALSE
|
|
|
|
#endif /* FM_PEDANTIC_DMA */
|
|
|
|
#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM
|
|
|
|
#define DEFAULT_dmaStopOnBusError FALSE
|
|
|
|
#define DEFAULT_stopAtBusError FALSE
|
|
|
|
#define DEFAULT_axiDbgNumOfBeats 1
|
|
|
|
#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
|
|
|
|
#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
|
|
|
|
#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
|
|
|
|
#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
|
|
|
|
#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT
|
|
|
|
#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC
|
|
|
|
#define DEFAULT_resetOnInit FALSE
|
2021-08-31 11:00:09 +00:00
|
|
|
#define DEFAULT_resetOnInitOverrideCallback NULL
|
2017-04-21 10:43:26 +00:00
|
|
|
#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */
|
|
|
|
#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */
|
|
|
|
#define DEFAULT_externalEccRamsEnable FALSE
|
|
|
|
#define DEFAULT_VerifyUcode FALSE
|
2021-08-31 11:00:09 +00:00
|
|
|
|
|
|
|
#if (DPAA_VERSION < 11)
|
|
|
|
#define DEFAULT_totalFifoSize(major, minor) \
|
|
|
|
(((major == 2) || (major == 5)) ? \
|
|
|
|
(100*KILOBYTE) : ((major == 4) ? \
|
|
|
|
(49*KILOBYTE) : (122*KILOBYTE)))
|
|
|
|
#define DEFAULT_totalNumOfTasks(major, minor) \
|
|
|
|
BMI_MAX_NUM_OF_TASKS
|
|
|
|
|
|
|
|
#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2)
|
|
|
|
#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4)
|
|
|
|
#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
|
|
|
|
#define DEFAULT_dmaCamNumOfEntries 32
|
|
|
|
#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
|
|
|
|
#define DEFAULT_dmaEnEmergency FALSE
|
|
|
|
#define DEFAULT_dmaSosEmergency 0
|
2017-04-21 10:43:26 +00:00
|
|
|
#define DEFAULT_dmaWatchdog 0 /* disabled */
|
2021-08-31 11:00:09 +00:00
|
|
|
#define DEFAULT_dmaEnEmergencySmoother FALSE
|
|
|
|
#define DEFAULT_dmaEmergencySwitchCounter 0
|
2017-04-21 10:43:26 +00:00
|
|
|
|
2021-08-31 11:00:09 +00:00
|
|
|
#define DEFAULT_dispLimit 0
|
|
|
|
#define DEFAULT_prsDispTh 16
|
|
|
|
#define DEFAULT_plcrDispTh 16
|
|
|
|
#define DEFAULT_kgDispTh 16
|
|
|
|
#define DEFAULT_bmiDispTh 16
|
|
|
|
#define DEFAULT_qmiEnqDispTh 16
|
|
|
|
#define DEFAULT_qmiDeqDispTh 16
|
|
|
|
#define DEFAULT_fmCtl1DispTh 16
|
|
|
|
#define DEFAULT_fmCtl2DispTh 16
|
|
|
|
|
|
|
|
#else /* (DPAA_VERSION < 11) */
|
|
|
|
/* Defaults are registers' reset values */
|
|
|
|
#define DEFAULT_totalFifoSize(major, minor) \
|
|
|
|
(((major == 6) && ((minor == 1) || (minor == 4))) ? \
|
|
|
|
(156*KILOBYTE) : (295*KILOBYTE))
|
|
|
|
|
|
|
|
/* According to the default value of FMBM_CFG2[TNTSKS] */
|
|
|
|
#define DEFAULT_totalNumOfTasks(major, minor) \
|
|
|
|
(((major == 6) && ((minor == 1) || (minor == 4))) ? 59 : 124)
|
|
|
|
|
|
|
|
#define DEFAULT_dmaCommQLow 0x2A
|
|
|
|
#define DEFAULT_dmaCommQHigh 0x3F
|
|
|
|
#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
|
|
|
|
#define DEFAULT_dmaCamNumOfEntries 64
|
|
|
|
#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
|
|
|
|
#define DEFAULT_dmaEnEmergency FALSE
|
|
|
|
#define DEFAULT_dmaSosEmergency 0
|
|
|
|
#define DEFAULT_dmaWatchdog 0 /* disabled */
|
|
|
|
#define DEFAULT_dmaEnEmergencySmoother FALSE
|
|
|
|
#define DEFAULT_dmaEmergencySwitchCounter 0
|
|
|
|
|
|
|
|
#define DEFAULT_dispLimit 0
|
|
|
|
#define DEFAULT_prsDispTh 16
|
|
|
|
#define DEFAULT_plcrDispTh 16
|
|
|
|
#define DEFAULT_kgDispTh 16
|
|
|
|
#define DEFAULT_bmiDispTh 16
|
|
|
|
#define DEFAULT_qmiEnqDispTh 16
|
|
|
|
#define DEFAULT_qmiDeqDispTh 16
|
|
|
|
#define DEFAULT_fmCtl1DispTh 16
|
|
|
|
#define DEFAULT_fmCtl2DispTh 16
|
|
|
|
#endif /* (DPAA_VERSION < 11) */
|
|
|
|
|
|
|
|
#define FM_TIMESTAMP_1_USEC_BIT 8
|
2017-04-21 10:43:26 +00:00
|
|
|
|
|
|
|
/**************************************************************************//**
|
2021-08-31 11:00:09 +00:00
|
|
|
@Collection Defines used for enabling/disabling FM interrupts
|
|
|
|
@{
|
2017-04-21 10:43:26 +00:00
|
|
|
*//***************************************************************************/
|
2021-08-31 11:00:09 +00:00
|
|
|
#define ERR_INTR_EN_DMA 0x00010000
|
|
|
|
#define ERR_INTR_EN_FPM 0x80000000
|
|
|
|
#define ERR_INTR_EN_BMI 0x00800000
|
|
|
|
#define ERR_INTR_EN_QMI 0x00400000
|
|
|
|
#define ERR_INTR_EN_PRS 0x00200000
|
|
|
|
#define ERR_INTR_EN_KG 0x00100000
|
|
|
|
#define ERR_INTR_EN_PLCR 0x00080000
|
|
|
|
#define ERR_INTR_EN_MURAM 0x00040000
|
|
|
|
#define ERR_INTR_EN_IRAM 0x00020000
|
|
|
|
#define ERR_INTR_EN_10G_MAC0 0x00008000
|
|
|
|
#define ERR_INTR_EN_10G_MAC1 0x00000040
|
|
|
|
#define ERR_INTR_EN_1G_MAC0 0x00004000
|
|
|
|
#define ERR_INTR_EN_1G_MAC1 0x00002000
|
|
|
|
#define ERR_INTR_EN_1G_MAC2 0x00001000
|
|
|
|
#define ERR_INTR_EN_1G_MAC3 0x00000800
|
|
|
|
#define ERR_INTR_EN_1G_MAC4 0x00000400
|
|
|
|
#define ERR_INTR_EN_1G_MAC5 0x00000200
|
|
|
|
#define ERR_INTR_EN_1G_MAC6 0x00000100
|
|
|
|
#define ERR_INTR_EN_1G_MAC7 0x00000080
|
|
|
|
#define ERR_INTR_EN_MACSEC_MAC0 0x00000001
|
|
|
|
|
|
|
|
#define INTR_EN_QMI 0x40000000
|
|
|
|
#define INTR_EN_PRS 0x20000000
|
|
|
|
#define INTR_EN_WAKEUP 0x10000000
|
|
|
|
#define INTR_EN_PLCR 0x08000000
|
|
|
|
#define INTR_EN_1G_MAC0 0x00080000
|
|
|
|
#define INTR_EN_1G_MAC1 0x00040000
|
|
|
|
#define INTR_EN_1G_MAC2 0x00020000
|
|
|
|
#define INTR_EN_1G_MAC3 0x00010000
|
|
|
|
#define INTR_EN_1G_MAC4 0x00000040
|
|
|
|
#define INTR_EN_1G_MAC5 0x00000020
|
|
|
|
#define INTR_EN_1G_MAC6 0x00000008
|
|
|
|
#define INTR_EN_1G_MAC7 0x00000002
|
|
|
|
#define INTR_EN_10G_MAC0 0x00200000
|
|
|
|
#define INTR_EN_10G_MAC1 0x00100000
|
|
|
|
#define INTR_EN_REV0 0x00008000
|
|
|
|
#define INTR_EN_REV1 0x00004000
|
|
|
|
#define INTR_EN_REV2 0x00002000
|
|
|
|
#define INTR_EN_REV3 0x00001000
|
|
|
|
#define INTR_EN_BRK 0x00000080
|
|
|
|
#define INTR_EN_TMR 0x01000000
|
|
|
|
#define INTR_EN_MACSEC_MAC0 0x00000001
|
|
|
|
/* @} */
|
2017-04-21 10:43:26 +00:00
|
|
|
|
|
|
|
/**************************************************************************//**
|
|
|
|
@Description Memory Mapped Registers
|
|
|
|
*//***************************************************************************/
|
|
|
|
|
|
|
|
#if defined(__MWERKS__) && !defined(__GNUC__)
|
|
|
|
#pragma pack(push,1)
|
|
|
|
#endif /* defined(__MWERKS__) && ... */
|
|
|
|
|
2021-08-31 11:00:09 +00:00
|
|
|
typedef struct
|
2017-04-21 10:43:26 +00:00
|
|
|
{
|
2021-08-31 11:00:09 +00:00
|
|
|
volatile uint32_t iadd; /**< FM IRAM instruction address register */
|
|
|
|
volatile uint32_t idata; /**< FM IRAM instruction data register */
|
|
|
|
volatile uint32_t itcfg; /**< FM IRAM timing config register */
|
|
|
|
volatile uint32_t iready; /**< FM IRAM ready register */
|
|
|
|
volatile uint32_t res[0x1FFFC];
|
|
|
|
} t_FMIramRegs;
|
|
|
|
|
|
|
|
/* Trace buffer registers -
|
|
|
|
each FM Controller has its own trace buffer residing at FM_MM_TRB(fmCtrlIndex) offset */
|
|
|
|
typedef struct t_FmTrbRegs
|
2017-04-21 10:43:26 +00:00
|
|
|
{
|
2021-08-31 11:00:09 +00:00
|
|
|
volatile uint32_t tcrh;
|
|
|
|
volatile uint32_t tcrl;
|
|
|
|
volatile uint32_t tesr;
|
|
|
|
volatile uint32_t tecr0h;
|
|
|
|
volatile uint32_t tecr0l;
|
|
|
|
volatile uint32_t terf0h;
|
|
|
|
volatile uint32_t terf0l;
|
|
|
|
volatile uint32_t tecr1h;
|
|
|
|
volatile uint32_t tecr1l;
|
|
|
|
volatile uint32_t terf1h;
|
|
|
|
volatile uint32_t terf1l;
|
|
|
|
volatile uint32_t tpcch;
|
|
|
|
volatile uint32_t tpccl;
|
|
|
|
volatile uint32_t tpc1h;
|
|
|
|
volatile uint32_t tpc1l;
|
|
|
|
volatile uint32_t tpc2h;
|
|
|
|
volatile uint32_t tpc2l;
|
|
|
|
volatile uint32_t twdimr;
|
|
|
|
volatile uint32_t twicvr;
|
|
|
|
volatile uint32_t tar;
|
|
|
|
volatile uint32_t tdr;
|
|
|
|
volatile uint32_t tsnum1;
|
|
|
|
volatile uint32_t tsnum2;
|
|
|
|
volatile uint32_t tsnum3;
|
|
|
|
volatile uint32_t tsnum4;
|
|
|
|
} t_FmTrbRegs;
|
|
|
|
|
2017-04-21 10:43:26 +00:00
|
|
|
#if defined(__MWERKS__) && !defined(__GNUC__)
|
|
|
|
#pragma pack(pop)
|
|
|
|
#endif /* defined(__MWERKS__) && ... */
|
|
|
|
|
|
|
|
/**************************************************************************//**
|
|
|
|
@Description General defines
|
|
|
|
*//***************************************************************************/
|
|
|
|
#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
|
2021-08-31 11:00:09 +00:00
|
|
|
#define FM_FW_DEBUG_INSTRUCTION 0x6ffff805UL
|
2017-04-21 10:43:26 +00:00
|
|
|
|
|
|
|
/**************************************************************************//**
|
|
|
|
@Description FPM defines
|
|
|
|
*//***************************************************************************/
|
|
|
|
/* masks */
|
2021-08-31 11:00:09 +00:00
|
|
|
#define FPM_BRKC_RDBG 0x00000200
|
|
|
|
#define FPM_BRKC_SLP 0x00000800
|
2017-04-21 10:43:26 +00:00
|
|
|
/**************************************************************************//**
|
|
|
|
@Description BMI defines
|
|
|
|
*//***************************************************************************/
|
|
|
|
/* masks */
|
|
|
|
#define BMI_INIT_START 0x80000000
|
2021-08-31 11:00:09 +00:00
|
|
|
#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000
|
2017-04-21 10:43:26 +00:00
|
|
|
#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
|
|
|
|
#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
|
|
|
|
#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
|
|
|
|
/**************************************************************************//**
|
|
|
|
@Description QMI defines
|
|
|
|
*//***************************************************************************/
|
|
|
|
/* masks */
|
|
|
|
#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
|
|
|
|
#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
|
|
|
|
#define QMI_INTR_EN_SINGLE_ECC 0x80000000
|
|
|
|
|
|
|
|
/**************************************************************************//**
|
|
|
|
@Description IRAM defines
|
|
|
|
*//***************************************************************************/
|
|
|
|
/* masks */
|
|
|
|
#define IRAM_IADD_AIE 0x80000000
|
|
|
|
#define IRAM_READY 0x80000000
|
|
|
|
|
2021-08-31 11:00:09 +00:00
|
|
|
/**************************************************************************//**
|
|
|
|
@Description TRB defines
|
|
|
|
*//***************************************************************************/
|
|
|
|
/* masks */
|
|
|
|
#define TRB_TCRH_RESET 0x04000000
|
|
|
|
#define TRB_TCRH_ENABLE_COUNTERS 0x84008000
|
|
|
|
#define TRB_TCRH_DISABLE_COUNTERS 0x8400C000
|
|
|
|
#define TRB_TCRL_RESET 0x20000000
|
|
|
|
#define TRB_TCRL_UTIL 0x00000460
|
2017-04-21 10:43:26 +00:00
|
|
|
typedef struct {
|
|
|
|
void (*f_Isr) (t_Handle h_Arg, uint32_t event);
|
|
|
|
t_Handle h_SrcHandle;
|
|
|
|
} t_FmanCtrlIntrSrc;
|
|
|
|
|
|
|
|
|
|
|
|
typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);
|
|
|
|
|
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
/***************************/
|
|
|
|
/* Master/Guest parameters */
|
|
|
|
/***************************/
|
|
|
|
uint8_t fmId;
|
|
|
|
e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];
|
|
|
|
uint16_t fmClkFreq;
|
2021-08-31 11:00:09 +00:00
|
|
|
uint16_t fmMacClkFreq;
|
|
|
|
t_FmRevisionInfo revInfo;
|
2017-04-21 10:43:26 +00:00
|
|
|
/**************************/
|
|
|
|
/* Master Only parameters */
|
|
|
|
/**************************/
|
|
|
|
bool enabledTimeStamp;
|
|
|
|
uint8_t count1MicroBit;
|
|
|
|
uint8_t totalNumOfTasks;
|
|
|
|
uint32_t totalFifoSize;
|
|
|
|
uint8_t maxNumOfOpenDmas;
|
|
|
|
uint8_t accumulatedNumOfTasks;
|
|
|
|
uint32_t accumulatedFifoSize;
|
|
|
|
uint8_t accumulatedNumOfOpenDmas;
|
|
|
|
uint8_t accumulatedNumOfDeqTnums;
|
|
|
|
#ifdef FM_LOW_END_RESTRICTION
|
|
|
|
bool lowEndRestriction;
|
|
|
|
#endif /* FM_LOW_END_RESTRICTION */
|
|
|
|
uint32_t exceptions;
|
2021-08-31 11:00:09 +00:00
|
|
|
uintptr_t irq;
|
|
|
|
uintptr_t errIrq;
|
2017-04-21 10:43:26 +00:00
|
|
|
bool ramsEccEnable;
|
|
|
|
bool explicitEnable;
|
|
|
|
bool internalCall;
|
|
|
|
uint8_t ramsEccOwners;
|
|
|
|
uint32_t extraFifoPoolSize;
|
|
|
|
uint8_t extraTasksPoolSize;
|
|
|
|
uint8_t extraOpenDmasPoolSize;
|
|
|
|
#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)
|
2021-08-31 11:00:09 +00:00
|
|
|
uint16_t portMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
|
2017-04-21 10:43:26 +00:00
|
|
|
uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
|
2021-08-31 11:00:09 +00:00
|
|
|
#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */
|
|
|
|
uint16_t portMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
|
2017-04-21 10:43:26 +00:00
|
|
|
uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
|
|
|
|
} t_FmStateStruct;
|
|
|
|
|
2021-08-31 11:00:09 +00:00
|
|
|
#if (DPAA_VERSION >= 11)
|
|
|
|
typedef struct t_FmMapParam {
|
|
|
|
uint16_t profilesBase;
|
|
|
|
uint16_t numOfProfiles;
|
|
|
|
t_Handle h_FmPort;
|
|
|
|
} t_FmMapParam;
|
|
|
|
|
|
|
|
typedef struct t_FmAllocMng {
|
|
|
|
bool allocated;
|
|
|
|
uint8_t ownerId; /* guestId for KG in multi-partition only,
|
|
|
|
portId for PLCR in any environment */
|
|
|
|
} t_FmAllocMng;
|
|
|
|
|
|
|
|
typedef struct t_FmPcdSpEntry {
|
|
|
|
bool valid;
|
|
|
|
t_FmAllocMng profilesMng;
|
|
|
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} t_FmPcdSpEntry;
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typedef struct t_FmSp {
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void *p_FmPcdStoragePrflRegs;
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t_FmPcdSpEntry profiles[FM_VSP_MAX_NUM_OF_ENTRIES];
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t_FmMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
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} t_FmSp;
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#endif /* (DPAA_VERSION >= 11) */
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typedef struct t_Fm
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2017-04-21 10:43:26 +00:00
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{
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/***************************/
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/* Master/Guest parameters */
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/***************************/
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/* locals for recovery */
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uintptr_t baseAddr;
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/* un-needed for recovery */
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t_Handle h_Pcd;
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char fmModuleName[MODULE_NAME_SIZE];
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char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE];
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t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS];
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t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */
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uint8_t guestId;
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/**************************/
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/* Master Only parameters */
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/**************************/
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/* locals for recovery */
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2021-08-31 11:00:09 +00:00
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struct fman_fpm_regs *p_FmFpmRegs;
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struct fman_bmi_regs *p_FmBmiRegs;
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struct fman_qmi_regs *p_FmQmiRegs;
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struct fman_dma_regs *p_FmDmaRegs;
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struct fman_regs *p_FmRegs;
|
2017-04-21 10:43:26 +00:00
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t_FmExceptionsCallback *f_Exception;
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t_FmBusErrorCallback *f_BusError;
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t_Handle h_App; /* Application handle */
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t_Handle h_Spinlock;
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bool recoveryMode;
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t_FmStateStruct *p_FmStateStruct;
|
2021-08-31 11:00:09 +00:00
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uint16_t tnumAgingPeriod;
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#if (DPAA_VERSION >= 11)
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t_FmSp *p_FmSp;
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uint8_t partNumOfVSPs;
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uint8_t partVSPBase;
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uintptr_t vspBaseAddr;
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#endif /* (DPAA_VERSION >= 11) */
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bool portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
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bool portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
|
2017-04-21 10:43:26 +00:00
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/* un-needed for recovery */
|
2021-08-31 11:00:09 +00:00
|
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struct fman_cfg *p_FmDriverParam;
|
2017-04-21 10:43:26 +00:00
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t_Handle h_FmMuram;
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|
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uint64_t fmMuramPhysBaseAddr;
|
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|
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bool independentMode;
|
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bool hcPortInitialized;
|
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|
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uintptr_t camBaseAddr; /* save for freeing */
|
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uintptr_t resAddr;
|
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uintptr_t fifoBaseAddr; /* save for freeing */
|
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|
|
t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */
|
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|
|
bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];
|
2021-08-31 11:00:09 +00:00
|
|
|
t_FmFirmwareParams firmware;
|
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|
|
bool fwVerify;
|
|
|
|
bool resetOnInit;
|
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|
|
t_FmResetOnInitOverrideCallback *f_ResetOnInitOverride;
|
|
|
|
uint32_t userSetExceptions;
|
2017-04-21 10:43:26 +00:00
|
|
|
} t_Fm;
|
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|
#endif /* __FM_H */
|