658 lines
16 KiB
C
Executable File
658 lines
16 KiB
C
Executable File
/*****************************************************************************
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*
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* This program is free software ; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* $Id: dyncode_arm.c 585 2006-01-16 09:48:55Z picard $
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*
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* The Core Pocket Media Player
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* Copyright (c) 2004-2005 Gabor Kovacs
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*
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****************************************************************************/
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#include "../common.h"
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#include "dyncode.h"
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#if defined(ARM) && defined(CONFIG_DYNCODE)
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void InstInit()
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{
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context* c = Context();
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c->NextCond = AL;
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c->NextSet = 0;
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c->NextByte = 0;
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c->NextHalf = 0;
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c->NextSign = 0;
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}
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void InstPost(dyninst* p)
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{
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context* c = Context();
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InstAdd(p,c);
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c->NextCond = AL;
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c->NextSet = 0;
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c->NextByte = 0;
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c->NextHalf = 0;
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c->NextSign = 0;
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}
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void Byte()
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{
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context* c = Context();
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c->NextByte = 1;
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c->NextSign = 0;
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}
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void Half()
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{
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context* c = Context();
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c->NextHalf = 1;
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c->NextSign = 0;
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}
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void SByte()
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{
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context* c = Context();
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c->NextByte = 1;
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c->NextSign = 1;
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}
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void SHalf()
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{
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context* c = Context();
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c->NextHalf = 1;
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c->NextSign = 1;
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}
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void C(int i)
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{
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context* c = Context();
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c->NextCond = i;
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}
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void S()
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{
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context* c = Context();
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c->NextSet = 1;
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}
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void IPLD(int* Code, reg* Dest)
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{
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context* c = Context();
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switch (*Code)
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{
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case PLD: c->NextCond=15; c->NextByte=1; *Code = LDR; *Dest=PC; break;
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case PLD_PRE: c->NextCond=15; c->NextByte=1; *Code = LDR_PRE; *Dest=PC; break;
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case PLD_POST: c->NextCond=15; c->NextByte=1; *Code = LDR_POST; *Dest=PC; break;
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case PLD_PRESUB: c->NextCond=15; c->NextByte=1; *Code = LDR_PRESUB; *Dest=PC; break;
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case PLD_POSTSUB: c->NextCond=15; c->NextByte=1; *Code = LDR_POSTSUB; *Dest=PC; break;
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}
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}
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#define MODE(x) ((uint32_t)(x) >> 28)
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#define MODEMASK ~0xF0000000
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void I3C(int Code, reg Dest, reg Op1, reg Op2,int Const)
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{
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context* c = Context();
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dyninst* p = NULL;
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if (MODE(Code) == 8 && Const>=0 && Const<8)
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{
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p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 12) | ((Op1 & 15) << 16) | ((Op2 & 15) << 0) | (Const << 20),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, 0);
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}
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InstPost(p);
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}
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void I3(int Code, reg Dest, reg Op1, reg Op2)
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{
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context* c = Context();
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if (MODE(Code) == 4)
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{
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dyninst* p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 0) | ((Op1 & 15) << 12) | ((Op2 & 15) << 16),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, 0);
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InstPost(p);
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}
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else
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if (MODE(Code) == 7)
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{
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dyninst* p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 12) | ((Op1 & 15) << 16) | ((Op2 & 15) << 0),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, 0);
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InstPost(p);
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}
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else
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I3S(Code,Dest,Op1,Op2,LSL,0);
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}
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void I3S(int Code, reg Dest, reg Op1, reg Op2, int ShiftType, int Shift)
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{
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context* c = Context();
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dyninst* p = NULL;
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if (Shift == 0)
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ShiftType = LSL;
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if (ShiftType == LSL && Shift < 0)
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{
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ShiftType = LSR;
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Shift = -Shift;
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}
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if ((ShiftType == LSR || ShiftType == ASR) && Shift < 0)
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{
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ShiftType = LSL;
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Shift = -Shift;
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}
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if (ShiftType == ROR && Shift < 0)
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Shift = Shift & 31;
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if (Shift >= 0 && Shift < 32)
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{
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if (Code >= 0 && Code < 16)
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{
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if (Code == CMP || Code == TST || Code == CMN || Code == TEQ)
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c->NextSet = 1;
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p = InstCreate32((c->NextCond << 28) | (Code << 21) | ((c->NextSet?1:0)<<20) |
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((Op1==NONE?R0:Op1) << 16) | ((Dest==NONE?R0:Dest) << 12) | (Shift << 7) | (ShiftType << 5) | (Op2),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, c->NextSet?1:0);
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}
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if (Shift == 0)
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{
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if (Code == MUL && Dest != Op1)
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{
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p = InstCreate32((c->NextCond << 28) | ((c->NextSet?1:0)<<20) |
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(Dest << 16) | (Op2 << 8) | 0x90 | (Op1),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, c->NextSet?1:0);
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}
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if (Code >= QADD && Code <= QDSUB)
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{
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p = InstCreate32((c->NextCond << 28) |
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(Dest << 12) | (Op1) | (Op2 << 16) | (0x5 << 4) | (1<<24) | ((Code-QADD)<<21),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, c->NextSet?1:0);
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}
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}
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IPLD(&Code,&Dest);
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if (Code == LDR || Code == STR ||
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Code == LDR_PRE || Code == STR_PRE ||
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Code == LDR_POST|| Code == STR_POST ||
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Code == LDR_PRESUB || Code == STR_PRESUB ||
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Code == LDR_POSTSUB || Code == STR_POSTSUB)
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{
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bool_t Pre = (Code != LDR_POST) && (Code != STR_POST) && (Code != LDR_POSTSUB) && (Code != STR_POSTSUB);
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bool_t PreWrite = (Code == LDR_PRE) || (Code == STR_PRE) || (Code == LDR_PRESUB) || (Code == STR_PRESUB);
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bool_t Load = (Code == LDR) || (Code == LDR_PRE) || (Code == LDR_POST) || (Code == LDR_PRESUB) || (Code == LDR_POSTSUB);
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bool_t Unsigned = (Code != LDR_PRESUB) && (Code != STR_PRESUB) && (Code != LDR_POSTSUB) && (Code != STR_POSTSUB);
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if (c->NextHalf || c->NextSign)
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{
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if (Shift==0 && (c->NextHalf || c->NextByte))
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p = InstCreate32((c->NextCond << 28) |
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((Pre?1:0)<<24) | (Unsigned<<23) |
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((PreWrite?1:0)<<21) | (Load<<20) | (c->NextSign << 6) | (c->NextHalf << 5) |
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(Op1 << 16) | (Dest << 12) | (9 << 4) | Op2,
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NONE, Op1, Op2, (c->NextCond != AL)?1:0, 0);
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}
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else
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p = InstCreate32((c->NextCond << 28) | (3 << 25) |
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((Pre?1:0)<<24) | (Unsigned<<23) | (c->NextByte<<22) |
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((PreWrite?1:0)<<21) | (Load<<20) |
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(Op1 << 16) | (Dest << 12) | (Shift << 7) | (ShiftType << 5) | Op2,
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NONE, Op1, Op2, (c->NextCond != AL)?1:0, 0);
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if (p)
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{
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if (Load)
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p->WrRegs |= 1 << Dest;
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else
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p->RdRegs |= 1 << Dest;
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if (!Pre || PreWrite)
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p->WrRegs |= 1 << Op1;
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}
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}
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}
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InstPost(p);
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}
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void I4(int Code, reg Dest, reg Op1, reg Op2, reg Op3)
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{
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context* c = Context();
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dyninst* p = NULL;
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if (Code == MLA)
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{
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p = InstCreate32((c->NextCond << 28) | (1 << 21) | ((c->NextSet?1:0)<<20) |
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(Dest << 16) | (Op3 << 12) | (Op2 << 8) | 0x90 | (Op1),
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Dest, Op1, Op2, (c->NextCond != AL)?1:0, c->NextSet?1:0);
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if (p) p->RdRegs |= 1 << Op3;
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}
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InstPost(p);
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}
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void IMul(reg Dest, reg Op1, int Mul)
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{
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if (Dest == Op1)
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InstPost(NULL); //assert
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switch (Mul)
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{
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case 0: I2C(MOV,Dest,NONE,0); break;
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case 1: I3(MOV,Dest,NONE,Op1); break;
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case 2: I3S(MOV,Dest,NONE,Op1,LSL,1); break;
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case 3: I3S(ADD,Dest,Op1,Op1,LSL,1); break;
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case 4: I3S(MOV,Dest,NONE,Op1,LSL,2); break;
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case 5: I3S(ADD,Dest,Op1,Op1,LSL,2); break;
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case 6: I3S(MOV,Dest,NONE,Op1,LSL,1); I3S(ADD,Dest,Dest,Dest,LSL,1); break; //2*3
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case 7: I3S(RSB,Dest,Op1,Op1,LSL,3); break;
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case 8: I3S(MOV,Dest,NONE,Op1,LSL,3); break;
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case 9: I3S(ADD,Dest,Op1,Op1,LSL,3); break;
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case 10: I3S(MOV,Dest,NONE,Op1,LSL,1); I3S(ADD,Dest,Dest,Dest,LSL,2); break; //2*5
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case 11: I3S(RSB,Dest,Op1,Op1,LSL,3); I3S(ADD,Dest,Dest,Op1,LSL,2); break; //7+4
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case 12: I3S(ADD,Dest,Op1,Op1,LSL,1); I3S(MOV,Dest,NONE,Dest,LSL,2); break; //3*4
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case 13: I3S(ADD,Dest,Op1,Op1,LSL,3); I3S(ADD,Dest,Dest,Op1,LSL,2); break; //9+4
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case 14: I3S(RSB,Dest,Op1,Op1,LSL,3); I3(ADD,Dest,Dest,Dest); break; //7*2
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case 15: I3S(RSB,Dest,Op1,Op1,LSL,4); break;
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case 16: I3S(MOV,Dest,NONE,Op1,LSL,4); break;
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case 17: I3S(ADD,Dest,Op1,Op1,LSL,4); break;
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default: I2C(MOV,Dest,NONE,Mul); I3(MUL,Dest,Op1,Dest); break;
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}
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}
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void IConst(reg Dest, int Const)
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{
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context* c = Context();
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dyninst* p = NULL;
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int Shift,Code;
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if (Const < 0)
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{
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Code = MVN;
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Const = -Const-1;
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}
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else
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Code = MOV;
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Const = (Const << 8) | ((Const >> 24) & 255);
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for (Shift=8;Shift<=32;Shift+=2)
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{
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if (Const & 0xC0)
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break;
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Const = (Const << 2) | ((Const >> 30) & 3);
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}
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Shift &= 31;
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Const &= 255;
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p = InstCreate32((c->NextCond << 28) | (1<<25) | (Code << 21) | ((c->NextSet?1:0)<<20) |
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(Dest << 12) | (Shift << 7) | Const,
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Dest, NONE, NONE, (c->NextCond != AL)?1:0, c->NextSet?1:0);
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InstPost(p);
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}
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void I2(int Code, reg Dest, reg Op1)
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{
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context* c = Context();
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if (MODE(Code) == 1)
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{
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dyninst* p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 16) | ((Op1 & 15) << 12),
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Dest, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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InstPost(p);
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}
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else
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if (MODE(Code) == 6)
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{
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dyninst* p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 12) | ((Op1 & 15) << 16),
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Dest, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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InstPost(p);
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}
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else
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I2C(Code,Dest,Op1,0);
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}
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void I2C(int Code, reg Dest, reg Op1, int Const)
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{
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int Shift;
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context* c = Context();
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dyninst* p = NULL;
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if (MODE(Code) == 2 && Const>=0 && Const<8)
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{
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p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 16) | ((Op1 & 15) << 12) | (Const << 0),
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Dest, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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}
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if (MODE(Code) == 9 && Const>=0 && Const<256)
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{
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p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 12) | ((Op1 & 15) << 16) | ((Const & 15) << 0) | ((Const & 0xF0) << 16),
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Dest, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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}
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if (MODE(Code) == 15)
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{
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if (Const<0)
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{
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Code ^= (1<<23);
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Const = -Const;
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}
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if (Code & 256) // dword or qword
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{
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if (Const & 3)
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Const = -1;
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else
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Const >>= 2;
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}
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if (Const>=0 && Const<256)
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{
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p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | ((Dest & 15) << 12) | ((Op1 & 15) << 16) | (Const << 0),
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NONE, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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if (Code & (1<<20))
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p->WrRegs |= 1 << Dest;
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else
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p->RdRegs |= 1 << Dest;
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if (!(Code & (1<<24)) || (Code & (1<<21)))
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p->WrRegs |= 1 << Op1;
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}
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}
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if (Code >= 0 && Code < 16)
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{
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if (Code == MOV && Const < 0)
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{
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Code = MVN;
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Const = -Const-1;
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}
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else
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if (Code == ADD && Const < 0)
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{
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Code = SUB;
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Const = -Const;
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}
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else
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if (Code == SUB && Const < 0)
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{
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Code = ADD;
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Const = -Const;
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}
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if (Code == CMP || Code == TST || Code == CMN || Code == TEQ)
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c->NextSet = 1;
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for (Shift = 0;Shift<32;Shift+=2)
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{
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if (Const >= 0 && Const <= 255)
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break;
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Const = (Const << 2) | ((Const >> 30) & 3);
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}
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if (Const >= 0 && Const <= 255)
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p = InstCreate32((c->NextCond << 28) | (1<<25) | (Code << 21) | ((c->NextSet?1:0)<<20) |
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((Op1==NONE?R0:Op1) << 16) | ((Dest==NONE?R0:Dest) << 12) | (Shift << 7) | Const,
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Dest, Op1, NONE, (c->NextCond != AL)?1:0, c->NextSet?1:0);
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}
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IPLD(&Code,&Dest);
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if (Code == LDR || Code == STR ||
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Code == LDR_PRE || Code == STR_PRE ||
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Code == LDR_POST|| Code == STR_POST ||
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Code == LDR_PRESUB || Code == STR_PRESUB ||
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Code == LDR_POSTSUB || Code == STR_POSTSUB)
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{
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bool_t Pre = (Code != LDR_POST) && (Code != STR_POST) && (Code != LDR_POSTSUB) && (Code != STR_POSTSUB);
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bool_t PreWrite = (Code == LDR_PRE) || (Code == STR_PRE) || (Code == LDR_PRESUB) || (Code == STR_PRESUB);
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bool_t Load = (Code == LDR) || (Code == LDR_PRE) || (Code == LDR_POST) || (Code == LDR_PRESUB) || (Code == LDR_POSTSUB);
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bool_t Unsigned = (Code != LDR_PRESUB) && (Code != STR_PRESUB) && (Code != LDR_POSTSUB) && (Code != STR_POSTSUB);
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if (Const == 0)
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{
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Pre = 1;
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PreWrite = 0;
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}
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if (Const < 0)
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{
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Const = -Const;
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Unsigned = !Unsigned;
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}
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if (c->NextHalf || c->NextSign)
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{
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if (Const >= 0 && Const < 256 && (c->NextHalf || c->NextByte))
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p = InstCreate32((c->NextCond << 28) |
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((Pre?1:0)<<24) | (Unsigned<<23) | (1 << 22) |
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((PreWrite?1:0)<<21) | (Load<<20) | (c->NextSign << 6) | (c->NextHalf << 5) |
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(Op1 << 16) | (Dest << 12) | ((Const >> 4) << 8) | (9 << 4) | (Const & 15),
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NONE, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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}
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else
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if (Const >= 0 && Const < 4096)
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p = InstCreate32((c->NextCond << 28) | (1 << 26) |
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((Pre?1:0)<<24) | (Unsigned<<23) | (c->NextByte<<22) |
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((PreWrite?1:0)<<21) | (Load<<20) |
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(Op1 << 16) | (Dest << 12) | Const,
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NONE, Op1, NONE, (c->NextCond != AL)?1:0, 0);
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if (p)
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{
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if (Load)
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p->WrRegs |= 1 << Dest;
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else
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p->RdRegs |= 1 << Dest;
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|
if (!Pre || PreWrite)
|
|
p->WrRegs |= 1 << Op1;
|
|
}
|
|
}
|
|
|
|
InstPost(p);
|
|
}
|
|
|
|
|
|
void I1P(int Code, reg Dest, dyninst* Block, int Ofs)
|
|
{
|
|
context* c = Context();
|
|
dyninst* p = NULL;
|
|
|
|
if (MODE(Code)==15)
|
|
{
|
|
p = InstCreate32((c->NextCond << 28) | (Code & MODEMASK) | (PC << 16) | ((Dest & 15) << 12),
|
|
Dest, PC, NONE, (c->NextCond != AL)?1:0, 0);
|
|
|
|
if (p)
|
|
{
|
|
p->Tag = Ofs;
|
|
p->ReAlloc = Block;
|
|
}
|
|
}
|
|
|
|
if (Code == LDR || Code == STR)
|
|
{
|
|
int Load = (Code == LDR);
|
|
|
|
p = InstCreate32((c->NextCond << 28) | (1 << 26) |
|
|
(1<<24) | (c->NextByte<<22) | (Load<<20) |
|
|
(PC << 16) | (Dest << 12),
|
|
Dest, PC, NONE, (c->NextCond != AL)?1:0, 0);
|
|
|
|
if (p)
|
|
{
|
|
p->Tag = Ofs;
|
|
p->ReAlloc = Block;
|
|
}
|
|
}
|
|
else
|
|
if (Code == MOV) // ADD|SUB,Dst,R15,Ofs
|
|
{
|
|
p = InstCreate32((c->NextCond << 28) |
|
|
(1<<25) | (PC << 16) | (Dest << 12),
|
|
Dest, PC, NONE, (c->NextCond != AL)?1:0, 0);
|
|
|
|
if (p)
|
|
{
|
|
p->Tag = Ofs;
|
|
p->ReAlloc = Block;
|
|
}
|
|
}
|
|
InstPost(p);
|
|
}
|
|
|
|
void I0P(int Code, int Cond, dyninst* Target)
|
|
{
|
|
dyninst* p = NULL;
|
|
if (Code == B || Code == BL)
|
|
{
|
|
p = InstCreate32((Cond << 28) | (5 << 25) | ((Code == BL?1:0)<<24),
|
|
PC, NONE, NONE, (Cond != AL)?1:0, 0);
|
|
if (p)
|
|
{
|
|
if (Code == BL)
|
|
p->WrRegs |= 1 << LR;
|
|
p->ReAlloc = Target;
|
|
p->Branch = 1;
|
|
}
|
|
}
|
|
InstPost(p);
|
|
}
|
|
|
|
void Break()
|
|
{
|
|
context* c = Context();
|
|
dyninst* p = InstCreate32((c->NextCond << 28) | (15 << 24),NONE,NONE,NONE,0,0);
|
|
if (p)
|
|
p->Branch = 1;
|
|
InstPost(p);
|
|
}
|
|
|
|
void CodeBegin()
|
|
{
|
|
int i;
|
|
dyninst* p = InstCreate32(0xE92D5FF0,SP,NONE,NONE,0,0);
|
|
if (p)
|
|
for (i=4;i<16;++i)
|
|
p->RdRegs |= 1 << i;
|
|
InstPost(p);
|
|
}
|
|
|
|
void CodeEnd()
|
|
{
|
|
int i;
|
|
dyninst* p = InstCreate32(0xE8BD9FF0,SP,NONE,NONE,0,0);
|
|
if (p)
|
|
for (i=4;i<16;++i)
|
|
p->WrRegs |= 1 << i;
|
|
InstPost(p);
|
|
}
|
|
|
|
bool_t InstReAlloc(dyninst* p,dyninst* ReAlloc)
|
|
{
|
|
int Diff = ReAlloc->Address - (p->Address+8);
|
|
int* Code = (int*) InstCode(p);
|
|
|
|
if (((*Code >> 25) & 7) == 6) //wldr,wstr
|
|
{
|
|
int Ofs = Diff + p->Tag;
|
|
int OfsUnsigned = 1;
|
|
if (Ofs < 0)
|
|
{
|
|
Ofs = -Ofs;
|
|
OfsUnsigned = 0;
|
|
}
|
|
if (*Code & 256)
|
|
{
|
|
if (Ofs & 3)
|
|
Ofs = 256;
|
|
else
|
|
Ofs >>= 2;
|
|
}
|
|
if (Ofs < 256)
|
|
{
|
|
*Code &= ~(1<<23);
|
|
*Code |= OfsUnsigned<<23;
|
|
*Code &= ~255;
|
|
*Code |= Ofs;
|
|
return 1;
|
|
}
|
|
|
|
DEBUG_MSG1(-1,T("Realloc failed for wldr,wstr %d"),Ofs);
|
|
}
|
|
else
|
|
if (((*Code >> 25) & 7) == 5) //branch
|
|
{
|
|
*Code &= 0xFF000000;
|
|
*Code |= (Diff >> 2) & ~0xFF000000;
|
|
return 1;
|
|
}
|
|
else
|
|
if (((*Code >> 25) & 7) == 1) //add dest,pc,#const
|
|
{
|
|
int Shift;
|
|
int Ofs = Diff + p->Tag;
|
|
|
|
*Code &= ~((15 << 21)|4095);
|
|
|
|
if (Ofs < 0)
|
|
{
|
|
Ofs = -Ofs;
|
|
*Code |= (SUB << 21);
|
|
}
|
|
else
|
|
*Code |= (ADD << 21);
|
|
|
|
for (Shift = 0;Shift<32;Shift+=2)
|
|
{
|
|
if (Ofs >= 0 && Ofs <= 255)
|
|
break;
|
|
Ofs = (Ofs << 2) | ((Ofs >> 30) & 3);
|
|
}
|
|
|
|
if (Ofs >= 0 && Ofs <= 255)
|
|
{
|
|
*Code |= (Shift << 7) | Ofs;
|
|
return 1;
|
|
}
|
|
|
|
DEBUG_MSG1(-1,T("Realloc failed for add dest,pc,#const %d"),Ofs);
|
|
}
|
|
else
|
|
if (((*Code >> 25) & 7) == 2) //ldr,str
|
|
{
|
|
int Ofs = Diff + p->Tag;
|
|
int OfsUnsigned = 1;
|
|
if (Ofs < 0)
|
|
{
|
|
Ofs = -Ofs;
|
|
OfsUnsigned = 0;
|
|
}
|
|
if (Ofs < 4096)
|
|
{
|
|
*Code &= ~(1<<23);
|
|
*Code |= OfsUnsigned<<23;
|
|
*Code &= ~4095;
|
|
*Code |= Ofs;
|
|
return 1;
|
|
}
|
|
|
|
DEBUG_MSG1(-1,T("Realloc failed for ldr,str %d"),Ofs);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#endif
|